AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 34

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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AD9268
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9268 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9268.
Various output test options are also provided to place predictable
values on the outputs of the AD9268.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9268 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A or
Channel B is placed in Register 0x24 and Register 0x25. If one
channel is chosen, its BIST signature is written to the two registers.
If both channels are chosen, the results from Channel A are placed
in the BIST signature registers.
Rev. A | Page 34 of 44
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

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