AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 38

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AD9268BCPZ-105

Manufacturer Part Number
AD9268BCPZ-105
Description
Dual 16 Bit 105 High SNR ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9268BCPZ-105

Design Resources
Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
Number Of Bits
16
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
590mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9268BCPZ-105
Manufacturer:
ADI
Quantity:
530
AD9268
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Address
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
0x0D
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Chip grade
(global)
Channel
index
Transfer
Power modes
(local)
Global clock
(global)
Clock divide
(global)
Test mode
(local)
Bit 7
(MSB)
0
Open
Open
Open
1
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(local)
0 = pdwn
1 = stndby
Open
Open
Reset PN
long gen
Speed grade ID
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Bit 4
1
Open
Open
Open
Open
Open
Reset
PN short
gen
Rev. A | Page 38 of 44
8-bit Chip ID[7:0]
(AD9268 = 0x32)
(default)
Open
Bit 3
1
Open
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Bit 1
LSB first
Open
Data
Channel
B
(default)
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
Open
Bit 0
(LSB)
0
Open
Data
Channel A
(default)
Transfer
Duty cycle
stabilizer
(default)
Default
Value
(Hex)
0x18
0x32
0x03
0x00
0x80
0x01
0x00
0x00
Default
Notes/
Comments
The nibbles
are mirrored
so LSB-first
mode or MSB-
first mode
registers
correctly,
regardless of
shift mode
Read only
Speed grade
ID used to
differentiate
devices; read
only
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to local
registers only
Synchronously
transfers data
from the
master shift
register to the
slave
Determines
various generic
modes of chip
operation
Clock divide
values other
than 000
automatically
cause the duty
cycle stabilizer
to become
active
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data

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