AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 41

• Manufacturer Part Number: AD9268BCPZ-105
• Description: Dual 16 Bit 105 High SNR ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9268BCPZ-105

• Design Resources: Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
• Number Of Bits: 16
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 590mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9268 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9268, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs (DRVDD).
For both AVDD and DRVDD several different decoupling capa-
citors should be used to cover both high and low frequencies.
Place these capacitors close to the point of entry at the PCB
level and close to the pins of the part, with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9268. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
The AD9268 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed,
using the SPI configuration registers after power-up. When the
AD9268 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current can be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9268, but it should be taken into account when consid-
ering the maximum DRVDD current for the part.
To avoid this additional DRVDD current, the AD9268 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed in LVDS mode via the SPI port, the OEB pin
can be taken low to enable the outputs.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD9268 exposed paddle, Pin 0.
Rev. A | Page 41 of 44
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged to
prevent solder wicking through the vias, which can compromise
the connection.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 67.
RBIAS
The AD9268 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9268 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
AN-772
Application Note, A Design and
AD9268