AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 53

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Transfer Format
Send byte format—the send byte protocol is used to set up the register address for subsequent commands.
S
Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.
S
Read byte format—the combined format of the send byte and the receive byte.
S
I²C Serial Port Timing
Table 42. I2C Timing Definitions
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
I2C
IDLE
HLD; STR
SET; STR
SET; STP
HLD; DAT
SET; DAT
LOW
HIGH
RISE
FALL
SPIKE
Slave Address
Slave
Address
Slave Address
Slave Address
SDA
SCL
t
FALL
W
S
A
W
t
HLD; STR
t
LOW
RAM Address
High Byte
A
Description
I²C clock frequency
Bus idle time between stop and start conditions
Hold time for repeated start condition
Setup time for repeated start condition
Setup time for stop condition
Hold time for data
Setup time for data
Duration of SCL clock low
Duration of SCL clock high
SCL/SDA rise time
SCL/SDA fall time
Voltage spike pulse width that must be suppressed by input filter
W
RAM Address
High Byte
R
t
t
RISE
SET; DAT
t
HLD; DAT
A
A
A
RAM Address High Byte
RAM Data 0
RAM Address
Low Byte
t
HIGH
A
RAM Address
Low Byte
t
Figure 60. I²C Serial Port Timing
FALL
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t
SET; STR
A
A
Sr
A
Slave
Address
RAM Data 1
Sr
RAM Data 0
t
A
HLD; STR
R
A
RAM Address Low Byte
A
RAM
Data 0
RAM Data 1
t
A
SPIKE
t
SET; STP
A
RAM Data 2
t
RISE
RAM
Data 1
A
P
RAM Data 2
t
IDLE
A
RAM
Data 2
AD9520-3
S
A
A
A
A
P
P
P
P