AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
POWER DISSIPATION
Table 15.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
Distribution Only Mode; VCO Divider On;
Distribution Only Mode; VCO Divider Off;
Maximum Power, Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
VCO Divider On/Off
REFIN (Differential) Off
REF1, REF2 (Single-Ended) On/Off
PLL Dividers and Phase Detector On/Off
LVDS Channel
LVDS Driver
CMOS Channel
CMOS Driver On/Off
Channel Divider Enabled
Zero Delay Block On/Off
One LVDS Output Enabled
One LVDS Output Enabled
Min
Typ
0.88
0.36
0.33
35
27
2.3
25
16
54
11
16
1.1
33
118
120
33
30
Max
1.0
0.43
0.4
1.3
50
43
8
43
31
22
67
146
15
154
30
40
35
Rev. 0 | Page 14 of 76
Unit
W
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
Does not include power dissipated in external resistors; all LVDS
outputs terminated with 100 Ω across differential pair; all CMOS
outputs have 10 pF capacitive loading
No clock; no programming; default register values
f
and output divider enabled; zero delay off
f
output and output divider enabled; zero delay off
PLL on; VCO divider = 3; all channel dividers on; 12 LVDS
outputs @ 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated in
termination resistors
PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-
down SYNC, 0x230[2] = 1b; power-down distribution reference,
0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one single-ended
reference enabled; double this number if both REF1 and REF2
are powered up
PLL off to PLL on, normal operation; no reference enabled
No LVDS output on to one LVDS output on; channel divider set to 1
Second LVDS output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; f
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
CLK
CLK
= 2.4 GHz; f
= 2.4 GHz; f
OUT
= 62.5 MHz and 10 pF of capacitive loading
OUT
OUT
= 200 MHz; VCO divider = 2; one LVDS output
= 200 MHz; VCO divider bypassed; one LVDS