AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 32

12- Channel Clock Generator With Integra

AD9522-5BCPZ

Manufacturer Part Number
AD9522-5BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9522-5BCPZ

Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Ic Interface Type
I2C, SPI
Frequency
2.4GHz
No. Of Outputs
12
No. Of Multipliers / Dividers
4
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9522-5
Table 25. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
f
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock
detect window bit (0x018[4]), the antibacklash pulse width
bit (0x017[1:0], see Table 2), and the lock detect counter
(0x018[6:5]). The lock and unlock detection values in Table 2
are for the nominal value of CPRSET = 5.1 kΩ. Doubling the
CPRSET value to 10 kΩ doubles the values in Table 2.
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference less than the lock
detect threshold. The lock detect circuit continues to indicate a
lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (0x018[6:5]).
Note that it is possible in certain low (<500 Hz) loop bandwidth,
high phase margin cases that the DLD can chatter during acqui-
sition, which can cause the AD9522 to automatically enter and exit
holdover. To avoid this problem, it is recommended that the
user make provisions for a capacitor to ground on the LD pin so
that current source digital lock detect (CSDLD) mode can be used.
REF
X = don’t care.
(MHz)
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
A
X
X
X
X
X
X
0
1
2
1
X
0
1
X
0
0
1
1
1
1
1
1
1
1
1
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
f
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
VCO
(MHz)
Rev. 0 | Page 32 of 76
Mode
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
FD
FD
FD
FD
FD
FD
Analog Lock Detect (ALD)
The AD9522 provides an ALD function that can be selected for
use at the LD pin. There are two operating modes for ALD.
The analog lock detect function requires an RC filter to provide a
logic level indicating lock/unlock. The ADIsimCLK tool can be
used to help the user select the right passive component values
for ALD to ensure its correct operation.
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source digital lock detect function.
N-channel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low going pulses. Lock is
indicated by the minimum duty cycle of the low going pulses.
P-channel open-drain lock detect. This signal requires a
pull-down resistor to GND. The output is normally low with
short, high going pulses. Lock is indicated by the minimum
duty cycle of the high going pulses.
Figure 31. Example of Analog Lock Detect Filter Using
Notes
P = 1, B = 1 (bypassed)
P = 2, B = 1 (bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P and P + 1 = 2 and 3, A = 0, B = 3
P and P + 1 = 2 and 3, A = 1, B = 3
P and P + 1 = 2 and 3, A = 2, B = 3
P and P + 1 = 2 and 3, A = 1, B = 4
P = 2, B = 5
P and P + 1 = 2 and 3, A = 0, B = 5
P and P + 1 = 2 and 3, A = 1, B = 5
P = 2, B = 6
P and P + 1 = 2 and 3, A = 0, B = 6
P and P + 1 = 4 and 5, A = 0, B = 3
P and P + 1 = 4 and 5, A = 1, B = 3
ALD
AD9522
N-Channel Open-Drain Driver
LD
R1
VS = 3.3V
R2
C
V
OUT

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