AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 39

12- Channel Clock Generator With Integra

AD9522-5BCPZ

Manufacturer Part Number
AD9522-5BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9522-5BCPZ

Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
800MHz
Ic Interface Type
I2C, SPI
Frequency
2.4GHz
No. Of Outputs
12
No. Of Multipliers / Dividers
4
Supply Voltage Range
3.135V To 3.465V
Digital Ic Case Style
LFCSP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9522-5BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
The channel dividers feeding the output drivers contain one
2-to-32 frequency divider. This divider provides for division-by-1
to division-by-32. Division-by-1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 43 through Table 54).
VCO Divider
The VCO divider provides frequency division between the CLK
input and the clock distribution channel dividers. The VCO
divider can be set to divide by 1, 2, 3, 4, 5, or 6 (see Table 50,
0x1E0[2:0]). However, when the VCO divider is set to 1, none
of the channel output dividers can be bypassed.
The VCO divider can also be set to static, which is useful for
applications where the only desired output frequency is the
CLK input frequency. Making the VCO divider static increases
the wideband spurious-free dynamic range (SFDR). The same
improvement in SFDR performance can also be achieved by
setting the VCO divider to 1.
Channel Dividers
A channel divider drives each group of three LVDS outputs.
There are four channel dividers (0, 1, 2, and 3) driving 12 LVDS
outputs (OUT0 to OUT11). Table 28 gives the register locations
used for setting the division and other functions of these dividers.
The division is set by the values of M and N. The divider can be
bypassed (equivalent to divide-by-1, divider circuit is powered
down) by setting the bypass bit. The duty-cycle correction can
be enabled or disabled according to the setting of the disable
divider DCC bits.
Table 28. Setting D
Divider
0
1
2
3
Channel Frequency Division (0, 1, 2, and 3)
For each channel (where the channel number x is 0, 1, 2, or 3),
the frequency division, D
(four bits each, representing Decimal 0 to Decimal 15), where
The high and low cycles are cycles of the clock signal currently routed
to the input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
Low Cycles M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
X
for the Output Dividers
X
, is set by the values of M and N
High Cycles N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]
X
= 1.
Bypass
0x191[7]
0x194[7]
0x197[7]
0x19A[7]
Disable
Div DCC
0x192[0]
0x195[0]
0x198[0]
0x19B[0]
Rev. 0 | Page 39 of 76
Otherwise, D
each channel divider to divide by any integer from 1 to 32.
Duty Cycle and Duty-Cycle Correction
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the disable divider DCC bit for
that channel.
Certain M and N values for a channel divider result in a non-
50% duty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle.
Duty-cycle correction requires the following channel divider
conditions:
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 29 to Table 32.
Table 29. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, odd
Even, odd
The M and N values for the channel
DCC enabled/disabled
VCO divider enabled/bypassed
The CLK input duty cycle
An even division must be set as M = N.
An odd division must be set as M = N + 1.
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
X
= (N + 1) + (M + 1) = N + M + 2. This allows
D
X
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/(N + M + 2)
(N + 1)/(N + M + 2)
Output Duty Cycle
AD9522-5
Disable Div
DCC = 0
50%
50%
50%
50%, requires
M = N
50%, requires
M = N + 1

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