AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 53

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are three operational codes: IO_UPDATE, end-of-data,
and pseudo-end-of-data. It is important that the EEPROM buffer
segment always have either an end-of-data or a pseudo-end-of-data
operational code and that an IO_UPDATE operation code appear
at least once before the end-of-data op code.
Register Section Definition Group
The register section definition group is used to define a continuous
register section for the EEPROM profile. It consists of three bytes.
The first byte defines how many continuous register bytes are in
this group. If the user puts 0x000 in the first byte, it means there
is only one byte in this group. If the user puts 0x001, it means
there are two bytes in this group. The maximum number of
registers in one group is 128.
The next two bytes are the low byte and high byte of the
memory address (16-bit) of the first register in this group.
IO_UPDATE (Operational Code 0x80)
The EEPROM controller uses Operational Code 0x80 to generate
an IO_UPDATE signal to update the active control register
bank from the buffer register bank during the download process.
At a minimum, there should be at least one IO_UPDATE
operational code after the end of the final register section definition
group. This is needed so that at least one IO_UPDATE occurs after
all of the AD9522 registers are loaded when the EEPROM is
read. If this operational code is absent during a write to the
EEPROM, the register values loaded from the EEPROM are not
transferred to the active register space, and these values do not
take effect after they are loaded from the EEPROM to the AD9522.
Table 41. Example of EEPROM Buffer Segment
Reg Addr (Hex)
Start EEPROM Buffer Segment
0xA00
0xA01
0xA02
0xA03
0xA04
0xA05
0xA06
0xA07
0xA08
0xA09
0xA0A
Bit 7 (MSB)
0
0
0
Bit 6
Address [15:8] of the second group of registers
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Address [7:0] of the second group of registers
Address [15:8] of the third group of registers
Bit 5
Address [15:8] of the first group of registers
Address [7:0] of the third group of registers
Address [7:0] of the first group of registers
IO_UPDATE operational code (0x80)
End-of-data operational code (0xFF)
Number of bytes [6:0] of the second group of registers
Number of bytes [6:0] of the third group of registers
Number of bytes [6:0] of the first group of registers
End-of-Data (Operational Code 0xFF)
The EEPROM controller uses Operational Code 0xFF to
terminate the data transfer process between EEPROM and the
control register during the upload and download process. The
last item appearing in the EEPROM buffer segment should be
either this operational code or the pseudo-end-of-data
operational code.
Pseudo-End-of-Data (Operational Code 0xFE)
The AD9522 EEPROM buffer segment has 23 bytes that can
contain up to seven register section definition groups. If users
want to define more than seven register section definition
groups, the pseudo-end-of-data operational code (0xFE) can be
used. During the upload process, when the EEPROM controller
receives the pseudo-end-of-data operational code, it halts the
data transfer process, clears the REG2EEPROM bit, and enables
the AD9522 serial port. Users can then program the EEPROM
buffer segment again and reinitiate the data transfer process by
setting the REG2EEPROM bit (0xB03[0]) to 1 and the
IO_UPDATE bit (0x232[0]) to 1. The internal I2C master then
begins writing to the EEPROM starting from the EEPROM address
held from the last writing.
This sequence enables more discrete instructions to be written
to the EEPROM than would otherwise be possible due to the
limited size of the EEPROM buffer segment. It also permits the
user to write to the same register multiple times with a different
value each time.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
AD9522-5