AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 56

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
Addr
(Hex)
01E
01F
Output Driver Control
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FD
0FE
to
18F
LVDS Channel Dividers
190
191
192
Parameter
PLL_Readback
(read-only)
OUT0 control
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control
OUT11 control
Enable output
on CSDLD
Enable output
on CSDLD
Divider 0
PLL_CTRL_9
Bit 7 (MSB)
OUT0 format
OUT1 format
OUT2 format
OUT3 format
OUT4 format
OUT5 format
OUT6 format
OUT7 format
OUT8 format
OUT9 format
OUT10 format
OUT11 format
CSDLD En
OUT7
Unused
Divider 0
bypass
Unused
Divider 0 low cycles
Bit 6
CSDLD En
OUT6
Unused
Divider 0
ignore
SYNC
OUT10 CMOS
OUT11 CMOS
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
configuration
OUT0 CMOS
OUT1 CMOS
OUT2 CMOS
OUT3 CMOS
OUT4 CMOS
OUT5 CMOS
OUT6 CMOS
OUT7 CMOS
OUT8 CMOS
OUT9 CMOS
Unused
Bit 5
Holdover
active
CSDLD En
OUT5
Unused
Divider 0
force
high
Unused
Rev. 0 | Page 56 of 76
Bit 4
REF2
selected
CSDLD En
OUT4
Unused
Divider 0
start high
OUT10 polarity
OUT11 polarity
OUT0 polarity
OUT1 polarity
OUT2 polarity
OUT3 polarity
OUT4 polarity
OUT5 polarity
OUT6 polarity
OUT7 polarity
OUT8 polarity
OUT9 polarity
Unused
Bit 3
CLK freq >
threshold
CSDLD En
OUT3
CSDLD En
OUT11
Bit 2
REF2
freq >
threshold
CSDLD En
OUT2
CSDLD En
OUT10
Channel 0
power-
down
Divider 0 high cycles
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
differential voltage
OUT10 LVDS
OUT11 LVDS
OUT0 LVDS
OUT1 LVDS
OUT2 LVDS
OUT3 LVDS
OUT4 LVDS
OUT5 LVDS
OUT6 LVDS
OUT7 LVDS
OUT8 LVDS
OUT9 LVDS
phase offset
Divider 0
Bit 1
Enable
zero delay
REF1 freq >
threshold
CSDLD En
OUT1
CSDLD En
OUT9
Reserved
Bit 0 (LSB)
Unused
Digital lock
detect
OUT0
LVDS
power-down
OUT1
LVDS
power-down
OUT2
LVDS
power-down
OUT3
LVDS
power-down
OUT4
LVDS
power-down
OUT5
LVDS
power-down
OUT6
LVDS
power-down
OUT7
LVDS
power-down
OUT8
LVDS
power-down
OUT9
LVDS
power-down
OUT10
LVDS
power-down
OUT11
LVDS
power-down
CSDLD En
OUT0
CSDLD En
OUT8
Divider 0
Disable
DCC
77
Default
Value
(Hex)
00
N/A
62
62
62
62
62
62
62
62
62
62
62
62
00
00
00
00
00