AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 6

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
Parameter
NOISE CHARACTERISTICS
PLL DIGITAL LOCK DETECT WINDOW
1
2
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
In-Band Phase Noise of the Charge Pump/
PLL Figure of Merit (FOM)
Lock Threshold (Coincidence of Edges)
Unlock Threshold (Hysteresis)
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
2
2
Min
Typ
−165
−162
−152
−144
−222
3.5
7.5
3.5
7
15
11
Rev. 0 | Page 6 of 76
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(f
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 11
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; lock
detect window settings can be varied by changing the
CPRSET resistor
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from unlock to lock)
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
0x017[1:0] = 10b; 0x018[4] = 0b
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from lock to unlock)
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
0x017[1:0] = 10b; 0x018[4] = 0b
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
PFD
) is an