AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 67

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01D
01D
01D
01D
01D
01E
01F
01F
01F
01F
01F
01F
[5]
[4]
[3]
[1]
[0]
[1]
[5]
[4]
[3]
[2]
[1]
[0]
Enable clock
doubler
Disable PLL
status register
Enable LD pin
comparator
Enable external
holdover
Enable
holdover
Enable zero
delay
Holdover active
(read-only)
REF2 selected
(read-only)
CLK frequency
> threshold
(read-only)
REF2 frequency
> threshold
(read-only)
REF1 frequency
> threshold
(read-only)
Digital lock
detect
(read-only)
Description
Enable PLL reference input clock doubler.
[5] = 0; doubler disabled (default).
[5] = 1; doubler enabled.
Disables the PLL status register readback.
[4] = 0; PLL status register enabled (default).
[4] = 1; PLL status register disabled. If this bit is set, 0x01F is not automatically updated.
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When the AD9522 is in internal (automatic) holdover mode, this enables the use of the voltage on the
LD pin to determine if the PLL was previously in a locked state (see Figure 34). Otherwise, this can be used
with the REFMON and STATUS pins to monitor the voltage on the LD pin.
[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover
controller treats this pin as true (high, default).
[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).
[1] = 1; external holdover mode, holdover controlled by SYNC pin.
Enables the internally controlled holdover function.
[0] = 0; holdover disabled (default).
[0] = 1; holdover enabled.
Enables zero delay function.
[1] = 0; disables zero delay function (default).
[1] = 1; enables zero delay function.
Readback register. Indicates if the part is in the holdover state (see Figure 34). This is not the same as
holdover enabled.
[5] = 0; not in holdover.
[5] = 1; holdover state active.
Readback register. Indicates which PLL reference is selected as the input to the PLL.
[4] = 0; REF1 selected (or differential reference if in differential mode).
[4] = 1; REF2 selected.
Readback register. Indicates if the external CLK input frequency is greater than the threshold (see Table 14,
REF1, REF2, and external CLK frequency status monitor parameter).
[3] = 0; CLK frequency is less than the threshold.
[3] = 1; CLK frequency is greater than the threshold.
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than the threshold frequency.
[2] = 1; REF2 frequency is greater than the threshold frequency.
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
set by Register 0x01A[6].
[1] = 0; REF1 frequency is less than the threshold frequency.
[1] = 1; REF1 frequency is greater than the threshold frequency.
Readback register. Digital lock detect.
[0] = 0; PLL is not locked.
[0] = 1; PLL is locked.
Rev. 0 | Page 67 of 76
AD9522-5