AD9522-5BCPZ Analog Devices Inc, AD9522-5BCPZ Datasheet - Page 68

• Manufacturer Part Number: AD9522-5BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-5BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 800MHz
• Ic Interface Type: I2C, SPI
• Frequency: 2.4GHz
• No. Of Outputs: 12
• No. Of Multipliers / Dividers: 4
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
Table 48. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name
0F0
0F0
0F0
0F0
0F0
0F1
0F2
0F3
0F4
0F5
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FC
0FC
0FC
0FC
[7]
[6:5]
[4:3]
[2:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[6]
[5]
[4]
[3]
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVDS
differential
voltage
OUT0 LVDS
power-down
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.
CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Description
Selects the output type for OUT0.
[7] = 0; LVDS (default).
[7] = 1; CMOS.
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
[6:5]
00
01
10
11 (default)
Sets the output polarity for OUT0.
[7]
0 (default)
0
1
1
1
1
Sets the LVDS output differential voltage (V
[2]
0
0 (default)
1
1
LVDS power-down.
[0] = 0; normal operation (default).
[0] = 1; power-down. Output driver is in a high impedance state.
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
[7]
0
1
1
OUT0A
Tristate
On
Tristate
On
[4]
X
X
0 (default)
0
1
1
[1]
0
1 (default)
0
1
CSDLD Signal OUT7 Enable Status
0
0
1
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Tristate
On
0
1
0 (default)
0
1
OUT0B
Tristate
On
[3]
1
I
1.75 (V
3.5 (V
5.25 (V
7.0 (V
Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enable OUT7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).
OD
(mA)
OD
OD
OD
OD
= 350 mV for 100 Ω termination across differential pair)
= 700 mV for 100 Ω termination across differential pair)
= 175 mV for 100 Ω termination across differential pair)
= 525 mV for 100 Ω termination across differential pair)
OD
).
Output Type
LVDS
LVDS
CMOS
CMOS
CMOS
CMOS
OUT0A
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
OUT0B
Inverting
Noninverting
Noninverting
Inverting
Inverting
Noninverting