ADE7569ASTZF16-RL Analog Devices Inc, ADE7569ASTZF16-RL Datasheet - Page 124
ADE7569ASTZF16-RL
Manufacturer Part Number
ADE7569ASTZF16-RL
Description
IC,Power Metering,QFP,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Specifications of ADE7569ASTZF16-RL
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE7569ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
- Current page: 124 of 136
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ADE7566/ADE7569
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double buffered receive and transmit registers. Figure 96
shows when the status and interrupt flags are raised. The transmit
interrupt occurs when the transmit shift register is loaded with
the data in the SPI/I
register. If the SPI master is in transmit operating mode, and the
SPI/I
been written with new data by the beginning of the next byte
transfer, the transmit operation stops.
When a new byte of data is received in the SPI/I
Buffer SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt
2
C Transmit Buffer SFR (SPI2CTx, 0x9A) register has not
2
C Transmit Buffer SFR (SPI2CTx, 0x9A)
SPICPHA = 1
SPICPHA = 0
WITH INTMOD = 1
WITH INTMOD = 0
WITH INTMOD = 1
WITH INTMOD = 0
(SPICPOL = 1)
(SPICPOL=0)
SPITx FLAGS
SPITx FLAGS
SPITx FLAGS
SPITx FLAGS
SPIRx AND
SPIRx AND
SPIRx AND
SPIRx AND
2
SCLK
SCLK
SS_b
C Receive
MISO
MOSI
MISO
MOSI
Figure 97. SPI Timing Configurations
Rev. PrA | Page 124 of 136
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
flag is raised. If the data in the SPI/I
(SPI2CRx, 0x9B) register is not read before new data is ready to
be loaded into the SPI/I
an overflow condition has occurred. This overflow condition,
indicated by the SPIRxOF flag, forces the new data to be discarded
or overwritten if the RxOFW bit is set.
TRANSMIT SHIFT REGISTER
TRANSMIT SHIFT REGISTER
Figure 96. SPI Receive and Transmit Interrupt and Status Flags
SPITx (EMPTY)
SPITx
STOPS TRANSFER IF TIMODE = 1
SPITxIRQ = 1
Preliminary Technical Data
2
C Receive Buffer SFR (SPI2CRx, 0x9B),
?
?
2
C Receive Buffer SFR
RECEIVE SHIFT REGISTER
RECEIVE SHIFT REGISTER
SPIRx (FULL)
SPIRx
SPIRxOF = 1
SPIRxIRQ = 1
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