ADE7755ARSZRL Analog Devices Inc, ADE7755ARSZRL Datasheet - Page 15

• Manufacturer Part Number: ADE7755ARSZRL
• Description: Energy Metering IC With Pulse Output
• Manufacturer: Analog Devices Inc

Specifications of ADE7755ARSZRL

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADE7755ZEB - BOARD EVALUATION FOR AD7755
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HPF and Offset Effects
Figure 29 shows the effect of offsets on the active power calculation.
An offset on Channel 1 and Channel 2 contributes a dc component
after multiplication. Because the dc component is extracted by
the LPF, it accumulates as active power. If not properly filtered, dc
offsets introduce error to the energy accumulation. This problem is
easily avoided by enabling the HPF (that is, the AC/ DC pin is
set to logic high) in Channel 1. By removing the offset from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at cos(ωt) are removed by the
LPF and the digital-to-frequency conversion (see the
Frequency Conversion
The HPF in Channel 1 has an associated phase response that is
compensated for on chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figure 30 and Figure 31 show the phase error between
channels with the compensation network activated. The ADE7755
is phase compensated up to 1 kHz, as shown. This ensures correct
active harmonic power calculation even at low power factors.
Figure 29. Effect of Channel Offset on the Active Power Calculation
–0.05
–0.10
V
{V cos(ωt) + V
V
0.30
0.25
0.20
0.15
0.10
0.05
OS
V
V × I
2
0
×
× I
2
×
2
0
Figure 30. Phase Error Between Channels (0 Hz to 1 kHz)
I
OS
I
+
×
100
0
V
cos(
OS
×
200
2
ω
I
OS
OS
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE
POWER CALCULATION
t
} × {I cos(ωt) + I
)
300
+
ω
section).
V
I
V
FREQUENCY (RAD/s)
OS
OS
OS
FREQUENCY (Hz)
400
× V
× I
×
I
500
cos(
2ω
ω
600
t
OS
)
} =
+
700
I
OS
×
800
V
cos(
900
Digital-to-
ω
1000
t
)
+
Rev. A | Page 15 of 20
DIGITAL-TO-FREQUENCY CONVERSION
The digital output of the low-pass filter after multiplication
contains the active power information. However, because this
LPF is not an ideal brick-wall filter implementation, the output
signal also contains attenuated components at the line frequency
and its harmonics, that is, cos(hωt) where h = 1, 2, 3, and so on.
The magnitude response of the filter is given by
For a line frequency of 50 Hz, the filter gives an attenuation
of the 2ω (100 Hz) component of approximately −22 dB. The
dominating harmonic is at twice the line frequency, that is,
cos(2 ωt), which is due to the instantaneous power signal.
Figure 32 shows the instantaneous active power signal at the
output of the LPF, which still contains a significant amount of
instantaneous power information, that is, cos(2 ωt). This signal
is then passed to the digital-to-frequency converter where it is
integrated (accumulated) over time to produce an output frequency.
This accumulation of the signal suppresses or averages out any
non-dc components in the instantaneous active power signal. The
average value of a sinusoidal signal is 0. Therefore, the frequency
generated by the ADE7755 is proportional to the average active
power. Figure 32 shows the digital-to-frequency conversion for
steady load conditions, that is, constant voltage and current.
–0.05
–0.10
H
0.30
0.25
0.20
0.15
0.10
0.05
(
0
Figure 31. Phase Error Between Channels (40 Hz to 70 Hz)
40
f
)
=
1
+
45
(
f
/
1
8.9
Hz
50
FREQUENCY (Hz)
)
55
60
65
ADE7755
70
(4)