ADE7758ARWZRL Analog Devices Inc, ADE7758ARWZRL Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADE7758ARWZRL
Manufacturer Part Number
ADE7758ARWZRL
Description
IC,Power Metering,SOP,24PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7758ARWZ.pdf
(72 pages)
Specifications of ADE7758ARWZRL
Input Impedance
380 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
8mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Meter Type
3 Phase
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7758ARWZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADE7758
Pin
No.
17
18
19
20
21
22
23
24
Mnemonic
VARCF
IRQ
CLKIN
CLKOUT
CS
DIN
SCLK
DOUT
Description
Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information
depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and
calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN
registers (see the Reactive Power Frequency Output section).
Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include: an active
energy register at half level, an apparent energy register at half level, and waveform sampling up to 26 kSPS (see
the Interrupts section).
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7758. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of
a few tens of picofarad should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s
data sheet for the load capacitance requirements
A crystal can be connected across this pin and CLKIN as previously described to provide a clock source for
the ADE7758. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or
a crystal is being used.
Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7758 to share the serial
bus with several other devices (see the Serial Interface section).
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK (see the Serial Interface
section).
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock
(see the Serial Interface section). The SCLK has a Schmidt-trigger input for use with a clock source that has a slow
edge transition time, for example, opto-isolator outputs.
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output
is normally in a high impedance state, unless it is driving data onto the serial data bus (see the Serial Interface
section).
Rev. D | Page 10 of 72