ADE7758ARWZRL Analog Devices Inc, ADE7758ARWZRL Datasheet - Page 69
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ADE7758ARWZRL
Manufacturer Part Number
ADE7758ARWZRL
Description
IC,Power Metering,SOP,24PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7758ARWZ.pdf
(72 pages)
Specifications of ADE7758ARWZRL
Input Impedance
380 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
8mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Meter Type
3 Phase
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7758ARWZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A)
The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the
corresponding flag in the interrupt status register is set. The IRQ pin goes active low if the corresponding bit in the interrupt mask
register is set. When the MCU services the interrupt, it must first carry out a read from the interrupt status register to determine the
source of the interrupt. All the interrupts in the interrupt status register stay at their logic high state after an event occurs. The state of the
interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read.
Table 24. Interrupt Status Register
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Interrupt
Flag
AEHF
REHF
VAEHF
SAGA
SAGB
SAGC
ZXTOA
ZXTOB
ZXTOC
ZXA
ZXB
ZXC
LENERGY
RESET
PKV
PKI
WFSM
REVPAP
REVPRP
SEQERR
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Event Description
Indicates that an interrupt was caused by a change in Bit 14 among any one of the three
WATTHR registers, that is, the WATTHR register is half full.
Indicates that an interrupt was caused by a change in Bit 14 among any one of the three
VARHR registers, that is, the VARHR register is half full.
Indicates that an interrupt was caused by a 0 to 1 transition in Bit 15 among any one of
the three VAHR registers, that is, the VAHR register is half full.
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A.
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B.
Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase A.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase B.
Indicates a detection of a rising edge zero crossing in the voltage channel of Phase C.
In line energy accumulation, indicates the end of an integration over an integer number of half-
line cycles (LINECYC). See the Calibration section.
Indicates that the 5 V power supply is below 4 V. Enables a software reset of the ADE7758 and sets
the registers back to their default values. This bit in the STATUS or RSTATUS register is logic high
for only one clock cycle after a reset event.
Indicates that an interrupt was caused when the selected voltage input is above the value
in the VPINTLVL register.
Indicates that an interrupt was caused when the selected current input is above the value
in the IPINTLVL register.
Indicates that new data is present in the waveform register.
Indicates that an interrupt was caused by a sign change in the watt calculation among any one
of the phases specified by the TERMSEL bits in the COMPMODE register.
Indicates that an interrupt was caused by a sign change in the VAR calculation among any one
of the phases specified by the TERMSEL bits in the COMPMODE register.
Indicates that an interrupt was caused by a zero crossing from Phase A followed not by the zero
crossing of Phase C but by that of Phase B.
Rev. D | Page 69 of 72
ADE7758