ADF4350BCPZ-RL Analog Devices Inc, ADF4350BCPZ-RL Datasheet
ADF4350BCPZ-RL
Specifications of ADF4350BCPZ-RL
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ADF4350BCPZ-RL Summary of contents
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FEATURES Output frequency range: 137.5 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16 output Typical rms jitter: 0.5 ps rms Power supply: 3 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus ...
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ADF4350 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 Transistor Count ........................................................................... 6 ESD ...
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SPECIFICATIONS SDV = V = 3.3 V ± 10%; AGND = DGND = VCO DD P temperature range is −40°C to +85°C. Table 1. Parameter REF CHARACTERISTICS IN Input ...
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ADF4350 Parameter NOISE CHARACTERISTICS VCO Phase-Noise Performance 6 7 Normalized In-Band Phase Noise Floor 8 In-Band Phase Noise 9 Integrated RMS Jitter Spurious Signals Due to PFD Frequency Level of Signal With RF Mute Enabled 1 AC coupling ensures AV ...
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TIMING CHARACTERISTICS SDV = V = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used VCO DD P otherwise noted. Table 2. ...
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ADF4350 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND. Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Data is clocked into the 32-bit shift ...
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ADF4350 Pin No. Mnemonic Description 22 R Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage SET bias at the R 25 where 5.1 kΩ SET ...
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TYPICAL PERFORMANCE CHARACTERISTICS –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 ...
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ADF4350 0 –20 –40 –60 –80 –100 –120 –140 –160 1k 10k 100k FREQUENCY (Hz) Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band 904 MHz, REF = 100 MHz, PFD = 800 kHz, Output Divide-by-4 OUT ...
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CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed, and SW1 and SW2 are opened. This ensures ...
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ADF4350 MUXOUT AND LOCK DETECT The output multiplexer on the ADF4350 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (for details, see Figure 26). Figure 19 ...
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The VCO shows variation the V V band and from band-to-band. It has been shown for wideband applications covering a wide frequency range (and changing output dividers) that a value of 33 MHz/V provides the most accurate ...
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ADF4350 REGISTER MAPS 16-BIT INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 0 N16 N15 N14 ...
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INTEGER VALUE (INT) DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 0 N16 N15 N14 N13 N12 N11 N10 ...
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ADF4350 LOW NOISE AND LOW SPUR MUXOUT MODES DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 0 L2 ...
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RESERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 D13 D12 ...
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ADF4350 REGISTER 0 Control Bits With Bits [C3:C1] set Register 0 is programmed. Figure 24 shows the input data format for programming this register. 16-Bit INT Value These sixteen bits set the INT value, which determines ...
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When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REF duty cycle. The phase noise degradation can much for the REF duty ...
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ADF4350 REGISTER 3 Control Bits With Bits [C3:C1] set Register 3 is programmed. Figure 27 shows the input data format for programming this register. CSR Enable Setting DB18 to 1 enables cycle slip reduction. This is ...
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INITIALIZATION SEQUENCE The following sequence of registers is the correct sequence for initial power-up of the ADF4350 after the correct application of voltages to the supply pins: • Register 5 • Register 4 • Register 3 • Register 2 • ...
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ADF4350 The programmable modulus is also very useful for multi- standard applications dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a great benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires ...
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FAST LOCK—LOOP FILTER TOPOLOGY To use fast-lock mode, the damping resistor in the loop filter is reduced to ¼ of its value while in wide bandwidth mode. To achieve the wider loop filter bandwidth, the charge pump current increases by ...
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ADF4350 SPUR CONSISTENCY AND FRACTIONAL SPUR OPTIMIZATION With dither off, the fractional spur pattern due to the quantiza- tion noise of the SDM also depends on the particular phase word with which the modulator is seeded. The phase word can ...
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APPLICATIONS INFORMATION DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 34 shows how Analog Devices, Inc., parts can be used to implement such a system. The circuit block diagram shows the AD9761 ...
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ADF4350 INTERFACING The ADF4350 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 32 bits that have been clocked into the appropriate register on each ...
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OUTPUT MATCHING There are a number of ways to match the output of the ADF4350 for optimum operation; the most basic is to use a 50 Ω resistor bypass capacitor of 100 pF is connected ...
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... Model Temperature Range 1 ADF4350BCPZ −40°C to +85°C 1 ADF4350BCPZ-RL −40°C to +85°C 1 ADF4350BCPZ-RL7 −40°C to +85°C 1 EVAL-ADF4350EB1Z RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07325-0-11/08(0) 5.00 BSC SQ 0 ...