ADSP-2189MBSTZ-266 Analog Devices Inc, ADSP-2189MBSTZ-266 Datasheet - Page 10

• Manufacturer Part Number: ADSP-2189MBSTZ-266
• Description: IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2189MBSTZ-266

• Interface: Host Interface, Serial Port
• Clock Rate: 66MHz
• Non-volatile Memory: External
• On-chip Ram: 192kB
• Voltage - I/o: 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 66
• Device Input Clock Speed: 66MHz
• Ram Size: 192KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.25V
• Operating Supply Voltage (max): 2.75/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2189MBSTZ266

ADSP-2189M
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2189M supports read
and write operations as well as four different data formats. The
byte memory uses data bits 15:8 for data. The byte memory
uses data bits 23:16 and address bits 13:0 to create a 22-bit
address. This allows up to a 4 meg × 8 (32 megabit) ROM or
RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait-state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table VI shows the data formats
supported by the BDMA circuit.
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
15 14 13 12 11 10 9
0
0
0
BMPAGE
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
0
Figure 9. BDMA Control Register
0
0
Table VI. Data Formats
BDMA CONTROL
0
8
0
7
0
BDMA
OVERLAY
BITS
6
0
5
0
Word Size
24
16
8
8
4
0
3
1
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
1
BTYPE
0
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
0
0
DM (0 3FE3)
Alignment
Full Word
Full Word
MSBs
LSBs
–10–
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait-states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
The BMWAIT field, which has four bits on ADSP-2189M,
allows selection of up to 15 wait-states for BDMA transfers.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2189M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
5. Host checks IACK line to see if the DSP has completed the
6. Host ends IDMA transfer.
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: Bits 14:8 must
be set to 0. If Bit 15 = 0, the value of bits 13:0 represent the
starting address of internal memory to be accessed and Bit 14
reflects PM or DM for access.
nal memory (PM or DM).
previous IDMA operation.
REV. A