ADUC7020BCPZ62I-RL Analog Devices Inc, ADUC7020BCPZ62I-RL Datasheet - Page 15

• Manufacturer Part Number: ADUC7020BCPZ62I-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7020BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7020QSZ - KIT DEV ADUC7020 QUICK STARTEVAL-ADUC7020MKZ - KIT MINI DEV FOR ADUC7026/7027
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
2
CS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
DOCS
SFS
t
t
UCLK
HCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
depends on the clock divider or CD bits in the PLLCON MMR. t
(POLARITY = 0)
(POLARITY = 1)
Description
CS to SCLOCK edge
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
Data output valid after CS edge
CS high after SCLOCK edge
SCLOCK
SCLOCK
MISO
MOSI
CS
t
DOCS
t
CS
1
t
DSU
MSB IN
2
2
t
MSB
DHD
t
SH
Figure 9. SPI Slave Mode Timing (Phase Mode = 0)
t
DF
t
DAV
HCLK
1
= t
t
SL
Rev. C | Page 15 of 96
1
UCLK
t
DR
BITS 6 TO 1
BITS 6 TO 1
/2
CD
; see Figure 57.
Min
(2 × t
1 × t
2 × t
0
ADuC7019/20/21/22/24/25/26/27/28/29
UCLK
UCLK
HCLK
) + (2 × t
LSB IN
UCLK
t
SR
)
LSB
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
t
SF
t
SFS
HCLK
HCLK
Max
25
12.5
12.5
12.5
12.5
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns