ADUC7020BCPZ62I-RL Analog Devices Inc, ADUC7020BCPZ62I-RL Datasheet - Page 67

• Manufacturer Part Number: ADUC7020BCPZ62I-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7020BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7020QSZ - KIT DEV ADUC7020 QUICK STARTEVAL-ADUC7020MKZ - KIT MINI DEV FOR ADUC7026/7027
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 98. COMIID0 Register
Name
COMIID0
COMIID0 is the interrupt identification register.
Table 99. COMIID0 MMR Bit Descriptions
Bit 2:1
Status Bits
00
11
10
01
00
Table 100. COMCON0 Register
Name
COMCON0
COMCON0 is the line control register.
Table 101. COMCON0 MMR Bit Descriptions
Bit
7
6
5
4
3
2
1:0
Table 102. COMCON1 Register
Name
COMCON1
COMCON1 is the modem control register.
Name
DLAB
BRK
SP
EPS
PEN
STOP
WLS
Bit 0
NINT
1
0
0
0
0
Address
0xFFFF0708
Address
0xFFFF070C
Address
0xFFFF0710
Description
Divisor latch access. Set by user to enable
access to the COMDIV0 and COMDIV1
registers. Cleared by user to disable access to
COMDIV0 and COMDIV1 and enable access to
COMRX and COMTX.
Set break. Set by user to force SOUT to 0.
Cleared to operate in normal mode.
Stick parity. Set by user to force parity to
defined values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
Even parity select bit. Set for even parity.
Cleared for odd parity.
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
Stop bit. Set by user to transmit 1.5 stop bits if the
word length is five bits or 2 stop bits if the
word length is six bits, seven bits, or eight bits.
The receiver checks the first stop bit only,
regardless of the number of stop bits selected.
Cleared by user to generate 1 stop bit in the
transmitted data.
Word length select:
00 = five bits, 01 = six bits, 10 = seven bits,
11 = eight bits.
Priority
N/A
1
2
3
4
Definition
No interrupt
Receive line
status
interrupt
Receive buffer
full interrupt
Transmit
buffer empty
interrupt
Modem status
interrupt
Default Value
0x01
Default Value
0x00
Default Value
0x00
Clearing
Operation
N/A
Read
COMSTA0
Read COMRX
Write data to
COMTX or
read COMIID
Read
COMSTA1
Access
R
Access
R/W
Access
R/W
Rev. C | Page 67 of 96
Table 103. COMCON1 MMR Bit Descriptions
Bit
7:5
4
3
2
1
0
Table 104. COMSTA0 Register
Name
COMSTA0
COMSTA0 is the line status register.
Table 105. COMSTA0 MMR Bit Descriptions
Bit
7
6
5
4
3
2
1
0
Table 106. COMSTA1 Register
Name
COMSTA1
COMSTA1 is a modem status register.
ADuC7019/20/21/22/24/25/26/27/28/29
Name
LOOPBACK
DTR
Name
PEN
STOP
RTS
TEMT
THRE
BI
FE
PE
OE
DR
Address
0xFFFF0714
Description
Reserved.
COMTX empty status bit. Set automatically if
COMTX is empty. Cleared automatically when
writing to COMTX.
COMTX and COMRX empty. Set automatically if
COMTX and COMRX are empty. Cleared automati-
cally when one of the registers receives data.
Break error. Set when SIN is held low for more than
the maximum word length. Cleared automatically.
Framing error. Set when an invalid stop bit occurs.
Cleared automatically.
Parity error. Set when a parity error occurs.
Cleared automatically.
Overrun error. Set automatically if data is over-
written before being read. Cleared automatically.
Data ready. Set automatically when COMRX is full.
Cleared by reading COMRX.
Address
0xFFFF0718
Description
Reserved.
Loopback. Set by user to enable loopback
mode. In loopback mode, SOUT (see Table 78)
is forced high. The modem signals are also
directly connected to the status inputs (RTS
to CTS and DTR to DSR). Cleared by user to
be in normal mode.
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
Stop bit. Set by user to transmit 1.5 stop bits
if the word length is five bits, or 2 stop bits if
the word length is six bits, seven bits, or
eight bits. The receiver checks the first stop
bit only, regardless of the number of stop bits
selected. Cleared by user to generate 1 stop
bit in the transmitted data.
Request to send. Set by user to force the RTS
output to 0. Cleared by user to force the RTS
output to 1.
Data terminal ready. Set by user to force the
DTR output to 0. Cleared by user to force the
DTR output to 1.
Default Value
0x60
Default Value
0x00
Access
R
Access
R