ADUC7020BCPZ62I-RL Analog Devices Inc, ADUC7020BCPZ62I-RL Datasheet - Page 77

• Manufacturer Part Number: ADUC7020BCPZ62I-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7020BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7020QSZ - KIT DEV ADUC7020 QUICK STARTEVAL-ADUC7020MKZ - KIT MINI DEV FOR ADUC7026/7027
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 151. PLAADC Register
Name
PLAADC
PLAADC is the PLA source for the ADC start conversion signal.
Table 152. PLAADC MMR Bit Descriptions
Bit
31:5
4
3:0
Table 153. PLADIN Register
Name
PLADIN
PLADIN is a data input MMR for PLA.
Value
0000
0001
1111
Address
0xFFFF0B48
Address
0xFFFF0B4C
Description
Reserved.
ADC start conversion enable bit. Set by user
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
ADC start conversion source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Default Value
0x00000000
Default Value
0x00000000
Access
R/W
Access
R/W
Rev. C | Page 77 of 96
Table 154. PLADIN MMR Bit Descriptions
Bit
31:16
15:0
Table 155. PLADOUT Register
Name
PLADOUT
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 156. PLADOUT MMR Bit Descriptions
Bit
31:16
15:0
Table 157. PLALCK Register
Name
PLALCK
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
ADuC7019/20/21/22/24/25/26/27/28/29
Description
Reserved.
Output bit from Element 15 to Element 0.
Address
0xFFFF0B50
Address
0xFFFF0B54
Description
Reserved.
Input bit to Element 15 to Element 0.
Default Value
0x00000000
Default Value
0x00
Access
R
Access
W