ADUC7020BCPZ62I-RL Analog Devices Inc, ADUC7020BCPZ62I-RL Datasheet - Page 88

IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC

ADUC7020BCPZ62I-RL

Manufacturer Part Number
ADUC7020BCPZ62I-RL
Description
IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7020BCPZ62I-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
44MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
PLA, PWM, PSM, Temp Sensor, WDT
Number Of I /o
14
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 5x12b; D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC7020QSZ - KIT DEV ADUC7020 QUICK STARTEVAL-ADUC7020MKZ - KIT MINI DEV FOR ADUC7026/7027
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ADuC7019/20/21/22/24/25/26/27/28/29
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the
ADuC7019/20/21/22/24/25/26/27/28/29-based designs to
achieve optimum performance from the ADCs and DAC.
Although the parts have separate pins for analog and digital
ground (AGND and IOGND), the user must not tie these to
two separate ground planes unless the two ground planes are
connected very close to the part. This is illustrated in the
simplified example shown in Figure 79a. In systems where
digital and analog ground planes are connected together
somewhere else (at the system power supply, for example), the
planes cannot be reconnected near the part because a ground
loop results. In these cases, tie all the ADuC7019/20/21/
22/24/25/26/27/28/29 AGND and IOGND pins to the analog
ground plane, as illustrated in Figure 79b. In systems with only
one ground plane, ensure that the digital and analog components
are physically separated onto separate halves of the board so
that digital return currents do not flow near analog circuitry
(and vice versa).
The ADuC7019/20/21/22/24/25/26/27/28/29 can then be
placed between the digital and analog sections, as illustrated in
Figure 79c.
In all of these scenarios, and in more complicated real-life
applications, the user should pay particular attention to the flow
of current from the supplies and back to ground. Make sure the
return paths for all currents are as close as possible to the paths
the currents took to reach their destinations.
b.
a.
c.
PLACE ANALOG
COMPONENTS
COMPONENTS HERE
COMPONENTS HERE
PLACE ANALOG
PLACE ANALOG
HERE
Figure 79. System Grounding Schemes
AGND
AGND
DGND
COMPONENTS HERE
COMPONENTS HERE
COMPONENTS HERE
PLACE DIGITAL
PLACE DIGITAL
PLACE DIGITAL
DGND
DGND
Rev. C | Page 88 of 96
For example, do not power components on the analog side (as
seen in Figure 79b) with IOV
currents from IOV
currents flowing under analog circuitry, which can occur if a
noisy digital chip is placed on the left half of the board (shown
in Figure 79c). If possible, avoid large discontinuities in the
ground plane(s) such as those formed by a long trace on the same
layer because they force return signals to travel a longer path. In
addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
When connecting fast logic signals (rise/fall time < 5 ns) to any of
the ADuC7019/20/21/22/24/25/26/27/28/29 digital inputs, add a
series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the part’s input pins. A value of 100 Ω or
200 Ω is usually sufficient to prevent high speed signals from
coupling capacitively into the part and affecting the accuracy of
ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/20/21/22/24/25/26/27/28/29
can be generated by the internal PLL or by an external clock
input. To use the internal PLL, connect a 32.768 kHz parallel
resonant crystal between XCLKI and XCLKO, and connect a
capacitor from each pin to ground as shown in Figure 80. The
crystal allows the PLL to lock correctly to give a frequency of
41.78 MHz. If no external crystal is present, the internal
oscillator is used to give a typical frequency of 41.78 MHz ± 3%.
To use an external source clock input instead of the PLL (see
Figure 81), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
Using an external clock source, the ADuC7019/20/21/22/24/
25/26/27/28/29-specified operational clock speed range is
50 kHz to 44 MHz ± 1%, which ensures correct operation of
the analog peripherals and Flash/EE.
Figure 80. External Parallel Resonant Crystal Connections
Figure 81. Connecting an External Clock Source
12pF
12pF
EXTERNAL
SOURCE
CLOCK
DD
32.768kHz
to flow through AGND. Avoid digital
XCLKO
XCLKO
XCLKI
XCLKI
XCLK
DD
45
44
because that forces return
ADuC7026
ADuC7026
TO
FREQUENCY
DIVIDER
TO
INTERNAL
PLL

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