CY7C1315KV18-250BZC Cypress Semiconductor Corp, CY7C1315KV18-250BZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1315KV18-250BZC
• Description: CY7C1315KV18-250BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1315KV18-250BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 18M (512K x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Contents
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Application Example ...................................................... 11
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
TAP Electrical Characteristics ...................................... 17
Document Number: 001-58904 Rev. *C
165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 5
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
Concurrent Transactions ........................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR II SRAM ........................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
Switching Characteristics .............................................. 26
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 29
Package Diagram ............................................................ 30
Acronyms ....................................................................... 31
Document Conventions ................................................. 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 24
Ordering Code Definitions ......................................... 29
Units of Measure ....................................................... 31
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
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