CYV15G0204TRB-BGXC Cypress Semiconductor Corp, CYV15G0204TRB-BGXC Datasheet - Page 10

• Manufacturer Part Number: CYV15G0204TRB-BGXC
• Description: IC,TV/VIDEO CIRCUIT,Data Serializer,BICMOS,BGA,256PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0204TRB-BGXC

• Function: Serializer/Deserializer
• Data Rate: 1.485Gbps
• Input Type: LVTTL
• Output Type: PECL
• Number Of Inputs: 4
• Number Of Outputs: 4
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number : 38-02101 Rev. *D
Pin Definitions
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
LDTDEN
ULCC
ULCD
SPDSELA
SPDSELB
SPDSELC
SPDSELD
INSELC
INSELD
LFIC
LFID
WREN
ADDR[3:0]
Notes
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.
Name
Device Configuration and Control Bus Signals
implemented by direct connection to V
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
(continued)
LVTTL input
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
3-Level Select
static control input
LVTTL Input,
asynchronous
LVTTL Output,
asynchronous
LVTTL input,
asynchronous,
internal pull-up
asynchronous,
internal pull-up
I/O Characteristics Signal Description
SS
[4]
(ground). The HIGH level is usually implemented by direct connection to V
Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level
Detector, Range Controller, and Transition Density Detector are all enabled to
determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream.
If the Signal Level Detector, Range Controller, or Transition Density Detector are out
of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx± until
such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure
the trip level of the Signal Level Detector. The Transition Density Detector limit is one
transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range
Controller is used to determine if the RXPLL tracks TRGCLKx± or the selected input
serial data stream. It is recommended to set LDTDEN = HIGH.
Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions for
a long period of time, or the high-gain differential serial inputs (INx±) are left floating,
there may be brief frequency excursions of the RXCLKx± outputs from TRGCLKx±.
Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range
of each channel’s transmit (channels A and B) or receive PLL (channels C and D).
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential Serial
Data Input, INx2±, is selected for the associated receive channel.
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the following
conditions is true:
Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[6:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
16
latches upon the assertion of RESET.
mapped in the device.
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCx is LOW
• Absence of TRGCLKx±.
lists the configuration latches within the device, and the initialization value of the
Table 5 on page 18
CC
CYV15G0204TRB
(power). The MID level is usually
shows how the latches are
[5]
[5]
Table 4 on page
Page 10 of 31
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