DSPIC33EP512MU810-E/PT Microchip Technology, DSPIC33EP512MU810-E/PT Datasheet - Page 290
DSPIC33EP512MU810-E/PT
Manufacturer Part Number
DSPIC33EP512MU810-E/PT
Description
100 PINS, 512KB Flash, 52KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 12x12x1mm T
Manufacturer
Microchip Technology
Series
dsPIC™ 33EPr
Datasheet
1.DSPIC33EP256MU810-IPF.pdf
(570 pages)
Specifications of DSPIC33EP512MU810-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
60 MIPs
Connectivity
CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
83
Program Memory Size
512KB (170K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
24K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33EP512MU810-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 16-22: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER
DS70616E-page 290
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
PHR
U-0
—
The blanking signal is selected via the BLANKSEL bits in the AUXCONx register.
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxH
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxH
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores rising edge of PWMxL
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores falling edge of PWMxL
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected Fault input
0 = Leading-Edge Blanking is not applied to selected Fault input
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to selected current-limit input
0 = Leading-Edge Blanking is not applied to selected current-limit input
Unimplemented: Read as ‘0’
BCH: Blanking in Selected Blanking Signal High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
BCL: Blanking in Selected Blanking Signal Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
R/W-0
PHF
U-0
—
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
BCH
PLR
R/W-0
R/W-0
BCL
PLF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLTLEBEN
R/W-0
R/W-0
BPHH
(1)
(1)
CLLEBEN
R/W-0
R/W-0
BPHL
2009-2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
BPLH
U-0
—
R/W-0
BPLL
U-0
—
bit 8
bit 0
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