DSPIC33FJ128MC706A-E/MR Microchip Technology, DSPIC33FJ128MC706A-E/MR Datasheet - Page 173

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE

DSPIC33FJ128MC706A-E/MR

Manufacturer Part Number
DSPIC33FJ128MC706A-E/MR
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706A-E/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
14.0
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The
support up to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
FIGURE 14-1:
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICx Pin
Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
dsPIC33FJXXXMCX06A/X08A/X10A
2: Some registers and associated bits
INPUT CAPTURE
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
12. “Input Capture” (DS70198) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Prescaler
(1, 4, 16)
Counter
3
INPUT CAPTURE BLOCK DIAGRAM
System Bus
ICxCON
dsPIC33FJXXXMCX06A/X08A/X10A
ICM<2:0> (ICxCON<2:0>)
ICOV, ICBNE (ICxCON<4:3>)
Mode Select
Edge Detection Logic
Clock Synchronizer
ICxI<1:0>
and
devices
Preliminary
(in IFSx Register)
Set Flag ICxIF
Interrupt
Logic
2.
3.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or exter-
nal clock.
Other operational features include the following:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Input capture can also be used to provide
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
additional sources of external interrupts
Note:
- Capture timer value on every rising edge of
Capture timer value on every edge (rising and
falling) of input at ICx pin
Prescaler Capture Event modes
- Capture timer value on every 4th rising edge
- Capture timer value on every 16th rising edge
4 buffer locations are filled
input at ICx pin
of input at ICx pin
of input at ICx pin
Logic
FIFO
R/W
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00).
From 16-Bit Timers
TMRy TMRz
1
ICxBUF
16
0
DS70594B-page 173
16
ICTMR
(ICxCON<7>)

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