DSPIC33FJ128MC706A-E/MR Microchip Technology, DSPIC33FJ128MC706A-E/MR Datasheet - Page 254

16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE

DSPIC33FJ128MC706A-E/MR

Manufacturer Part Number
DSPIC33FJ128MC706A-E/MR
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC706A-E/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 22-9:
REGISTER 22-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW
DS70594B-page 254
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
PCFG31
PCFG23
PCFG15
PCFG7
R/W-0
R/W-0
R/W-0
R/W-0
2:
3:
4:
2:
3:
4:
On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on the device.
ADC2 only supports analog inputs, AN0-AN15; therefore, no ADC2 port Configuration register exists.
PCFGx = ANx, where x = 16 through 31.
The PCFGx bits have no effect if the ADC module is disabled by setting the ADxMD bit in the PMDx
register. In this case, all port pins multiplexed with ANx will be in Digital mode.
On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on the device.
On devices with two analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the configuration
of port pins multiplexed with AN0-AN15.
PCFGx = ANx, where x = 0 through 15.
The PCFGx bits have no effect if the ADC module is disabled by setting the ADxMD bit in the PMDx
register. In this case, all port pins multiplexed with ANx will be in Digital mode.
PCFG<31:16>: ADC Port Configuration Control bits
1 = Port pin in Digital mode; port read input enabled; ADC input multiplexer connected to AV
0 = Port pin in Analog mode; port read input disabled; ADC samples pin voltage
PCFG<15:0>: ADC Port Configuration Control bits
1 = Port pin in Digital mode; port read input enabled; ADC input multiplexer connected to AV
0 = Port pin in Analog mode; port read input disabled; ADC samples pin voltage
PCFG30
PCFG22
PCFG14
PCFG6
R/W-0
R/W-0
R/W-0
R/W-0
ADxPCFGH: ADCx PORT CONFIGURATION REGISTER HIGH
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
PCFG29
PCFG21
PCFG13
PCFG5
R/W-0
R/W-0
R/W-0
R/W-0
PCFG28
PCFG20
PCFG12
PCFG4
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PCFG27
PCFG19
PCFG11
PCFG3
R/W-0
R/W-0
R/W-0
R/W-0
PCFG26
PCFG18
PCFG10
PCFG2
R/W-0
R/W-0
R/W-0
R/W-0
 2009 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
PCFG25
PCFG17
PCFG9
PCFG1
R/W-0
R/W-0
R/W-0
R/W-0
(1,2,3,4)
(1,2,3,4)
PCFG24
PCFG16
PCFG8
PCFG0
R/W-0
R/W-0
R/W-0
R/W-0
SS
SS
bit 8
bit 0
bit 8
bit 0

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