DSPIC33FJ16MC101-E/P Microchip Technology, DSPIC33FJ16MC101-E/P Datasheet - Page 150
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DSPIC33FJ16MC101-E/P
Manufacturer Part Number
DSPIC33FJ16MC101-E/P
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 PDIP .300in TUB
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16MC101-E/P
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16MC101-E/P
Manufacturer:
MICROCHIP
Quantity:
12 000
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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
14.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 14-1
Compare modes.
compare operation for various modes. The user
TABLE 14-1:
FIGURE 14-2:
DS70652C-page 150
OCM<2:0>
Continuous Pulse Mode
000
001
010
011
100
101
110
111
Active-High One-Shot
Active-Low One-Shot
(OCM = 110 or 111)
Delayed One-Shot
Output Compare Modes
lists the different bit settings for the Output
(OCM = 011)
(OCM = 100)
Toggle Mode
(OCM = 101)
(OCM = 001)
(OCM = 010)
PWM Mode
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle Mode
Delayed One-Shot
Continuous Pulse mode
PWM mode without fault
protection
PWM mode with fault protection 0, if OCxR is zero
OUTPUT COMPARE MODES
TMRy
Figure 14-2
OUTPUT COMPARE OPERATION
OCxRS
OCxR
Mode
Output Compare
Mode enabled
illustrates the output
Current output is maintained
0, if OCxR is zero
1, if OCxR is non-zero
1, if OCxR is non-zero
Controlled by GPIO register
Preliminary
OCx Pin Initial State
Timer is reset on
period match
0
1
0
0
application must disable the associated timer when
writing to the output compare control registers to avoid
malfunctions.
Note:
See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual”
OCxRS register restrictions.
OCx Rising edge
OCx Falling edge
OCx Rising and Falling edge
OCx Falling edge
OCx Falling edge
No interrupt
OCFA Falling edge for OC1 to OC4
OCx Interrupt Generation
(DS70209)
© 2011 Microchip Technology Inc.
—
for
OCxR
and
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