DSPIC33FJ16MC304-H/PT Microchip Technology, DSPIC33FJ16MC304-H/PT Datasheet
DSPIC33FJ16MC304-H/PT
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DSPIC33FJ16MC304-H/PT Summary of contents
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... Microchip Technology Inc. dsPIC33FJ16MC304 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70283H ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Output Compare (up to two channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2011 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Controller: • 5-cycle latency • available interrupt sources • three external interrupts • Seven programmable priority levels • ...
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... Motor Control Peripherals: • 6-channel 16-bit Motor Control PWM: - Three duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge-aligned or center-aligned - Manual output override control - One Fault input - Trigger for ADC conversions - PWM frequency for 16-bit resolution ...
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... PIC33FJ32MC202/204 and ds dsPIC33FJ16MC304 Product Families The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES Device Pins dsPIC33FJ32MC202 dsPIC33FJ32MC204 44 32 ...
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... Pin Diagrams 28-PIN SDIP, SOIC, SSOP AN0/V +/CN2/RA0 REF AN1/V REF (1) PGED1/AN2/C2IN-/RP0 (1) PGEC1/AN3/C2IN+/RP1 (1) AN4/RP2 (1) AN5/RP3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 (1) SOSCI/RP4 SOSCO/T1CK/CN0/RA4 (1) PGED3/ASDA1/RP5 /CN27/RB5 (2) 28-Pin QFN-S (1) PGED1/EMUD1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/EMUC1/AN3/C2IN+/RP1 /CN5/RB1 (1) AN4/RP2 /CN6/RB2 (1) AN5/RP3 /CN7/RB3 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals ...
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... Pin Diagrams (Continued) (2) 44-Pin QFN 22 (1) AN4/RP2 /CN6/RB2 23 (1) AN5/RP3 /CN7/RB3 24 (1) AN6/RP16 /CN8/RC0 25 (1) AN7/RP17 /CN9/RC1 26 (1) AN8/RP18 /CN10/RC2 OSC1/CLKI/CN30/RA2 30 OSC2/CLKO/CN29/RA3 31 TDO/RA8 32 (1) SOSCI/RP4 /CN1/RB4 33 34 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. ...
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... Pin Diagrams (Continued) 44-Pin TQFP (1) AN4/RP2 /CN6/RB2 23 (1) 24 AN5/RP3 /CN7/RB3 (1) 25 AN6/RP16 /CN8/RC0 (1) 26 AN7/RP17 /CN9/RC1 (1) 27 AN8/RP18 /CN10/RC2 OSC1/CLKI/CN30/RA2 31 OSC2/CLKO/CN29/RA3 32 TDO/RA8 (1) 33 SOSCI/RP4 /CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. DS70283H-page 8 11 ...
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... Table of Contents dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 31 5.0 Flash Program Memory.............................................................................................................................................................. 57 6.0 Resets ....................................................................................................................................................................................... 63 7.0 Interrupt Controller ..................................................................................................................................................................... 71 8.0 Oscillator Configuration ............................................................................................................................................................ 103 9 ...
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... TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices not intended comprehensive refer- ence source. To complement the infor- mation in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www ...
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... FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Buffer Pin Name PPS Type Type AN0-AN8 I Analog No CLKI I ST/CMOS No CLKO O — No OSC1 I ST/CMOS No OSC2 I/O — No SOSCI I ST/CMOS No SOSCO O — No CN0-CN30 IC1-IC2 I ST Yes IC7-IC8 I ST Yes OCFA I ST Yes OC1-OC2 O — ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name PPS Type Type INDX I ST Yes QEA I ST Yes QEB I ST Yes UPDN O CMOS Yes I ST Yes FLTA1 PWM1L1 O — No PWM1H1 O — No PWM1L2 O — No PWM1H2 O — No PWM1L3 O — ...
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... Basic Connection Requirements Getting started with the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
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... FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION V 10 µ MCLR C dsPIC33F 0.1 µF Ceramic 0.1 µF 10 Ω Ceramic 2.2.1 TANK CAPACITORS On boards with power traces running longer than six inches in length suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source ...
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... ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to ...
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... Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first ...
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... C compiler efficiency. For most instructions, the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle result, three parameter instructions can be supported, allowing operations to be executed in a single cycle ...
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... Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt ...
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... FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG ...
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... CPU Control Registers REGISTER 3-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared ...
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... REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) ...
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... REGISTER 3-2: CORCON: CORE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 SATA SATB SATDW bit 7 Legend Clear only bit R = Readable bit W = Writable bit 0’ = Bit is cleared ‘x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ ...
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... The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70283H-page 26 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled) ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... NOTES: DS70283H-page 30 © 2011 Microchip Technology Inc. ...
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... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAPS FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES dsPIC33FJ32MC202/204 0x000000 GOTO Instruction 0x000002 ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) DS70283H-page 32 4.1.2 INTERRUPT AND TRAP VECTORS All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices reserve the addresses between 0x00000 and organized in 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code ...
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... To maintain backward compatibility with PIC devices and improve data space memory usage efficiency, the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 instruction set supports both word and byte operations consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified ...
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... FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES WITH 2 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 0x0001 2 Kbyte SRAM Space 0x0FFF 0x1001 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70283H-page 34 ...
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... X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A — CN30PUE CN29PUE — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32MC204 and dsPIC33FJ16MC304 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...
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TABLE 4-10: QEI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name — QEI1CON 01E0 CNTERR QEISIDL INDEX DFLT1CON 01E2 — — — — POS1CNT 01E4 MAX1CNT 01E6 Legend uninitialized bit, — = unimplemented, ...
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TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC ...
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TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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... TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. TABLE 4-22: PORTC REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISC — ...
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TABLE 4-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... In addition to its use as a working register, the W15 register in the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown ...
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... TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 4.3.3 MOVE AND ACCUMULATOR INSTRUCTIONS ...
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... Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code typical in many DSP algorithms. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers ...
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... FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70283H-page 52 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value ...
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... Interfacing Program and Data Memory Spaces The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data ...
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... READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V ground (V ) and Master Clear (MCLR) ...
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... RTSP Operation The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. ...
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... REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER (1) (1) R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 (1) U-0 R/W-0 U-0 — ERASE bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation ...
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... REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Settable Only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
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... PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY Programmers can program one row of program Flash memory at a time this necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
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... EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000, W0 ...
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... RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
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... REGISTER 6-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... REGISTER 6-1: RCON: RESET CONTROL REGISTER bit 1 BOR: Brown-out Reset Flag bit Brown-out Reset has occurred Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit Power-on Reset has occurred Power-on Reset has not occurred Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset ...
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... System Reset The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
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... FIGURE 6-2: SYSTEM RESET TIMING V POR POR 1 POR 2 BOR SYSRST Oscillator Clock FSCM Device Status Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until V crosses the BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V ...
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... TABLE 6-2: OSCILLATOR DELAY Symbol V POR threshold POR T POR extension time POR V BOR threshold BOR T BOR extension time BOR T Programmable power-up time delay PWRT T Fail-Safe Clock Monitor Delay FSCM Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc ...
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... FIGURE 6-3: BROWN-OUT SITUATIONS V DD SYSRST V DD SYSRST V dips before PWRT expires SYSRST 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset ...
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... Configuration Mismatch Reset To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs. ...
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... Reset process. to the The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine ...
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... FIGURE 7-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 ...
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... TABLE 7-1: INTERRUPT VECTORS Interrupt Vector Request (IRQ) IVT Address Number Number 8 0 0x000014 9 1 0x000016 10 2 0x000018 11 3 0x00001A 12 4 0x00001C 13 5 0x00001E 14 6 0x000020 15 7 0x000022 16 8 0x000024 17 9 0x000026 18 10 0x000028 19 11 0x00002A 20 12 0x00002C ...
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... TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 ...
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... Interrupt Control and Status Registers dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement a total of 22 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
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... REGISTER 7-1: SR: CPU STATUS REGISTER R-0 R-0 R/C bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
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... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR bit 15 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘ ...
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... REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit ...
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... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
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... REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © ...
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... REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 83
... REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 U-0 U-0 FLTA1IF — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit ...
Page 84
... REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 85
... REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 86
... REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283H-page 86 © 2011 Microchip Technology Inc. ...
Page 87
... REGISTER 7-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 88
... REGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 U-0 FLTA1IE — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit ...
Page 89
... REGISTER 7-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ ...
Page 90
... REGISTER 7-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 91
... REGISTER 7-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 92
... REGISTER 7-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 93
... REGISTER 7-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP< ...
Page 94
... REGISTER 7-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
Page 95
... REGISTER 7-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 — IC8IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP< ...
Page 96
... REGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP< ...
Page 97
... REGISTER 7-20: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PWM1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 10-8 QEIIP< ...
Page 98
... REGISTER 7-21: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 R/W-1 R/W-0 — FLTA1IP<2:0> bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP< ...
Page 99
... REGISTER 7-23: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — PWM2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 8-10 FLTA2IP< ...
Page 100
... REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR< ...
Page 101
... Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source at initialization: 1. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source ...
Page 102
... NOTES: DS70283H-page 102 © 2011 Microchip Technology Inc. ...
Page 103
... Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. FIGURE 8-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator (P ) OSC OSC1 ( ...
Page 104
... CPU Clocking System The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 devices provide seven system clock options: • Fast RC (FRC) Oscillator • FRC Oscillator with PLL • Primary (XT EC) Oscillator • Primary Oscillator with PLL • Secondary (LP) Oscillator • Low-Power RC (LPRC) Oscillator • ...
Page 105
... XT with PLL. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0.8-8 MHz. FIGURE 8-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. TABLE 8-1: ...
Page 106
... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 107
... REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator ...
Page 108
... REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 109
... REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) ...
Page 110
... REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN< ...
Page 111
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different ...
Page 112
... NOTES: DS70283H-page 112 © 2011 Microchip Technology Inc. ...
Page 113
... POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices not intended reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power Savings Modes” (DS70196) the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 114
... IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9 ...
Page 115
... REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 — — T3MD bit 15 R/W-0 U-0 R/W-0 I2C1MD — U1MD bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 116
... REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 IC8MD IC7MD — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IC8MD: Input Capture 8 Module Disable bit ...
Page 117
... REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 118
... NOTES: DS70283H-page 118 © 2011 Microchip Technology Inc. ...
Page 119
... I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices not intended comprehensive refer- ence source. To complement the infor- mation in this data sheet, refer to Section 10. “I/O Ports” (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 120
... Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ16MC304 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Depending on the device ...
Page 121
... Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device ...
Page 122
... TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A PWM1 Fault PWM2 Fault QEI1 Phase A QEI1 Phase B ...
Page 123
... Output Mapping In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. ...
Page 124
... CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • ...
Page 125
... Peripheral Pin Select Registers The dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 family of devices implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK See Section 10.6.3.1 “Control Register Lock” ...
Page 126
... REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 127
... REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 128
... REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 129
... REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 130
... REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 131
... REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 132
... REGISTER 10-9: RPINR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 133
... REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 134
... REGISTER 10-11: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 135
... REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 136
... REGISTER 10-13: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ ...
Page 137
... REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 138
... REGISTER 10-16: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 139
... REGISTER 10-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 140
... REGISTER 10-20: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 141
... REGISTER 10-22: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 142
... REGISTER 10-24: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 143
... REGISTER 10-26: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 144
... NOTES: DS70283H-page 144 © 2011 Microchip Technology Inc. ...
Page 145
... TIMER1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the dsPIC33F/PIC24H Family Manual, which is available from the Microchip website (www ...
Page 146
... REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 147
... TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 148
... FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 149
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync Sync TMR2 Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70283H-page 149 ...
Page 150
... REGISTER 12-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2/3 ...
Page 151
... REGISTER 12-2: T3CON CONTROL REGISTER R/W-0 U-0 R/W-0 (2) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (2) — TGATE TCKPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set (2) bit 15 TON: Timer3 On bit 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimplemented: Read as ‘ ...
Page 152
... NOTES: DS70283H-page 152 © 2011 Microchip Technology Inc. ...
Page 153
... INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) of the “dsPIC33F/PIC24H Family Refer- ence Manual”, which is available from the Microchip website (www ...
Page 154
... Input Capture Registers REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 155
... OUTPUT COMPARE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output (DS70209) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 156
... Output Compare Modes Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes ...
Page 157
... REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Cleared in Hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 158
... NOTES: DS70283H-page 158 © 2011 Microchip Technology Inc. ...
Page 159
... MOTOR CONTROL PWM MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Motor Control PWM” (DS70187) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 160
... FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM1CON2 P1DTCON1 P1DTCON2 P1FLTACON P1OVDCON P1TMR Comparator P1TPER P1TPER Buffer P1TCON Comparator P1SECMP PWM Time Base Note: Details of PWM Generator #1and #2 are not shown for clarity. DS70283H-page 160 PWM Enable and Mode SFRs ...
Page 161
... FIGURE 15-2: 2-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM2) PWM2CON1 PWM2CON2 P2DTCON1 P2DTCON2 P2FLTACON P2OVDCON P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2011 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFRs ...
Page 162
... REGISTER 15-1: P TCON: PWM TIME BASE CONTROL REGISTER x R/W-0 U-0 R/W-0 PTEN — PTSIDL bit 15 R/W-0 R/W-0 R/W-0 PTOPS<3:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTEN: PWM Time Base Timer Enable bit ...
Page 163
... REGISTER 15-2: P TMR: PWM TIMER COUNT VALUE REGISTER x R-0 R/W-0 R/W-0 PTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) ...
Page 164
... REGISTER 15-4: P SECMP: SPECIAL EVENT COMPARE REGISTER x R/W-0 R/W-0 R/W-0 (1) SEVTDIR bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit Special Event Trigger will occur when the PWM time base is counting downward ...
Page 165
... REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-1 (1) — PEN3H PEN2H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 166
... REGISTER 15-6: PWM CON2: PWM CONTROL REGISTER 2 x U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ ...
Page 167
... REGISTER 15-7: P DTCON1: DEAD-TIME CONTROL REGISTER 1 x R/W-0 R/W-0 R/W-0 DTBPS<1:0> bit 15 R/W-0 R/W-0 R/W-0 DTAPS<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock period for Dead-Time Unit ...
Page 168
... REGISTER 15-8: P DTCON2: DEAD-TIME CONTROL REGISTER 2 x U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — DTS3A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ ...
Page 169
... REGISTER 15-9: P FLTACON: FAULT A CONTROL REGISTER x U-0 U-0 R/W-0 — — FAOV3H bit 15 R/W-0 U-0 U-0 FLTAM — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FAOVxH< ...
Page 170
... REGISTER 15-10: P OVDCON: OVERRIDE CONTROL REGISTER x U-0 U-0 R/W-1 — — POVD3H bit 15 U-0 U-0 R/W-0 — — POUT3H bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 POVDxH< ...
Page 171
... REGISTER 15-11: P DC1: PWM DUTY CYCLE REGISTER 1 x R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC1<15:0>: PWM Duty Cycle 1 Value bits REGISTER 15-12: P1DC2: PWM DUTY CYCLE REGISTER 2 ...
Page 172
... NOTES: DS70283H-page 172 © 2011 Microchip Technology Inc. ...
Page 173
... QUADRATURE ENCODER INTERFACE (QEI) MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Quadrature Interface (QEI)” (DS70208) of the “ ...
Page 174
... Control and Status Registers The QEI module has four user-accessible registers, accessible in either Byte or Word mode: • Control/Status Register (QEICON) – Allows control of the QEI operation and status flags indicating the module state. • Digital Filter Control Register (DFLTCON) – ...
Page 175
... REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER R/W-0 U-0 R/W-0 CNTERR — QEISIDL bit 15 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CNTERR: Count Error Status Flag bit ...
Page 176
... REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) bit 2 POSRES: Position Counter Reset Enable bit ...
Page 177
... REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 QEOUT QECK<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV< ...
Page 178
... NOTES: DS70283H-page 178 © 2011 Microchip Technology Inc. ...
Page 179
... SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Interface (SPI)” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 180
... REGISTER 17-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 U-0 R/C-0 U-0 — SPIROV — bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 181
... REGISTER 17-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (2) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 182
... REGISTER 17-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode) ...
Page 183
... REGISTER 17-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 184
... NOTES: DS70283H-page 184 © 2011 Microchip Technology Inc. ...
Page 185
... INTER-INTEGRATED 2 CIRCUIT™ (I C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit™ C™)” (DS70195) “ ...
Page 186
... FIGURE 18-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70283H-page 186 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 187
... REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Unimplemented bit, read as ‘0’ Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module ...
Page 188
... REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit ...
Page 189
... REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0 HS R/C-0 HS R-0 HSC IWCOL I2COV D_A bit 7 Legend Unimplemented bit, read as ‘0’ Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 190
... REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 191
... REGISTER 18-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 192
... NOTES: DS70283H-page 192 © 2011 Microchip Technology Inc. ...
Page 193
... The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC33FJ32MC202/204 dsPIC33FJ16MC304 device family. The UART is a full-duplex asynchronous system communicate with peripheral devices, such as personal computers, LIN, and RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and ® ...
Page 194
... REGISTER 19-1: UxMODE: UART R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Hardware Clearable R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 195
... REGISTER 19-1: UxMODE: UART bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits ...
Page 196
... REGISTER 19-2: U STA: UART x R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 197
... REGISTER 19-2: U STA: UART x bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only Receiver is Idle ...
Page 198
... NOTES: DS70283H-page 198 © 2011 Microchip Technology Inc. ...
Page 199
... ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) of the “dsPIC33F/PIC24H Family Reference Manual” ...
Page 200
... FIGURE 20-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND dsPIC33FJ32MC204 DEVICES AN0 AN8 CHANNEL SCAN CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 V REFL CH0NA CH0NB AN0 AN3 CH123SA CH123SB (2) CH1 AN6 V REFL CH123NA CH123NB AN1 AN4 CH123SA CH123SB (2) CH2 AN7 ...