DSPIC33FJ256GP510A-I/PT Microchip Technology, DSPIC33FJ256GP510A-I/PT Datasheet - Page 187
DSPIC33FJ256GP510A-I/PT
Manufacturer Part Number
DSPIC33FJ256GP510A-I/PT
Description
16 Bit MCU/DSP 40MIPS 256KB FLASH 100 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
2.DSPIC33FJ256GP506A-IPT.pdf
(8 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP510A-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
85
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
32-chx10-bit|32-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP510A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206A-IMR PDF datasheet
- DSPIC33FJ256GP506A-IPT PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 187 of 350
- Download datasheet (6Mb)
REGISTER 16-3:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: Read as ‘0’
This bit must not be set to ‘1’ by the user application.
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
dsPIC33FJXXXGPX06A/X08A/X10A
W = Writable bit
‘1’ = Bit is set
FRMPOL
R/W-0
U-0
—
U-0
U-0
—
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
R/W-0
U-0
—
DS70593C-page 187
U-0
U-0
—
—
bit 8
bit 0
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