DSPIC33FJ256MC710T-I/PT Microchip Technology, DSPIC33FJ256MC710T-I/PT Datasheet
DSPIC33FJ256MC710T-I/PT
Specifications of DSPIC33FJ256MC710T-I/PT
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DSPIC33FJ256MC710T-I/PT Summary of contents
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... Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on Device and Revision IDs for your specific device. © 2010 Microchip Technology Inc. dsPIC33FJXXXMCX06/X08/X10 For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ ...
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... Restart or Stop event. ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero. (2) Revision ID for Silicon Revision 0x3002 0x3004 0x3040 Affected (1) Revisions © 2010 Microchip Technology Inc. ...
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... Match Mode Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. Issue Summary The address error trap, stack error trap, math error trap, and DMA error trap will not wake-up a device from Doze mode. ...
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... When the UART module is operating in 8-bit mode ® (PDSEL = 0x) and using the IrDA encoder/decoder (IREN = 1), the module incorrectly transmits a data payload of 80h as 00h. Affected (1) Revisions devices, the © 2010 Microchip Technology Inc. ...
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... Sleep Mode Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. Issue Summary The WAKIF bit in the CxINTF register cannot be cleared by software instruction after the device has been interrupted from Sleep by activity on the CAN bus. ...
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... CPU does make writes before the ADC module does, then any attempts by the ADC module to write to these registers will fail. Work around In Doze mode, avoid writing code that will modify SFRs that may be written to by enabled peripherals. Affected Silicon Revisions DS80447D-page 6 © 2010 Microchip Technology Inc. ...
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... ADC Accuracy – Measurements taken with Internal V AD21aa INL -2 AD22aa DNL -1.5 AD23aa GERR 5 AD24aa EOFF 3 AD33a FNYQ — AD34a ENOB 9.5 AD56a FCNV — AD57a TSAMP — © 2010 Microchip Technology Inc. impedance is to ensure AD ADC 7 Typical Max. — 200 12 bits — — 2 — — 2 — 1 ...
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... T — AD Units Conditions Ohm 10-bit +/V - REF REF Bits — LSB — LSB — LSB — LSB — +/V - REF REF LSB — LSB — LSB — LSB — kHz — Bits — ksps — — — © 2010 Microchip Technology Inc. ...
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... C30>Use Alternate Settings) Affected Silicon Revisions © 2010 Microchip Technology Inc. 5. Module: CPU The DISI instruction will not disable interrupts when a DISI instruction is executed in the same instruction assembly, the decrements to zero. For example, when user code executes a DISI #7, interrupts for cycles (7 + the DISI instruction itself) are disabled ...
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... SPIEN bit, clear the SPI interrupt flag (SPIxIF), perform a dummy read of the SPIxBUF register, and return from the Interrupt Service Routine (ISR). the method If DMA is being used, no work around exists. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. 12. Module: ECAN The ECAN module (ECAN1 or ECAN2) does not function correctly in Loopback mode. Work around Do not use Loopback mode. Affected Silicon Revisions ...
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... If a UTXISEL0 value of ‘1’ is needed, avoid using read-modify-write instructions on the UxSTA register. Copy the UxSTA register to a temporary variable and set UxSTA<13> prior to performing read- modify-write operations. Copy the new value back to the UxSTA register. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... If the IWCOL bit is set, it must be cleared in software, and I2CxTRN register must be rewritten. Affected Silicon Revisions © 2010 Microchip Technology Inc. 2 24. Module The ACKSTAT bit (I2CxSTAT<15>) reflects the received ACK/NACK status transmissions, but not for slave transmissions result, a slave cannot use this bit to determine whether it received an ACK or a NACK from a master ...
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... Table 5. Work around None. Affected Silicon Revisions A2 X Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C < TA < +85°C for industrial Min. Typical Max. Units -3 — Conditions (1,2) -40°C < TA < +85° 3.0-3.6V DD © 2010 Microchip Technology Inc. ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. 32. Module: Device ID Register On a few devices, the content of the Device ID register can change from the factory programmed default value immediately after RTSP or ICSP™ Flash programming result, development tools will not recognize these devices and will generate an error message ...
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... The first interrupt occurs at the beginning of the Start bit and the second occurs after reception of the Sync field character. Work around If an extra interrupt is detected, ignore the additional interrupt. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... Affected Silicon Revisions © 2010 Microchip Technology Inc. 40. Module: DMA When the DMA channel is configured for One Shot mode mode with NULL write enabled, the channel will write an extra NULL to the peripheral register after completing the last transfer. In the case of the SPI ...
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... Work around Use 16-bit operations to clear BCL. Affected Silicon Revisions © 2010 Microchip Technology Inc. 2 46. Module there are two I C devices on the bus, one of them acts as the master receiver and the other acts as the slave transmitter. If both devices are configured for 10-bit Addressing mode, and have ...
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... UART error interrupt fails to occur. Affected Silicon Revisions 53. Module: UART When the UART is operating in 8-bit mode (PDSEL = 0x) and using the IrDA decoder (IREN = 1), the module incorrectly transmits a data payload of 80h as 00h. Work around None. Affected Silicon Revisions ® encoder © 2010 Microchip Technology Inc. ...
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... © 2010 Microchip Technology Inc. 56. Module: PWM Under certain conditions, devices in the motor control family have a glitch in the PWMxL signal. The glitch is a brief high pulse during the low portion of the duty cycle. This error occurs when the module is configured in Single-Shot mode (PTMOD< ...
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... PxTCON register), the motor control PWM module generates more interrupts than expected. Work around Do not use Doze mode with the motor control PWM if the time base output postscaler is different than 1:1. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... IFSxbits.QEIIF = 0; POSCNT_b15 ^= 0x8000; // Overflow or Underflow } © 2010 Microchip Technology Inc. Work around To prevent this condition from occurring, set MAXCNT to 0x7FFF, which will cause an interrupt to be generated by the QEI module. In addition, a global variable could be used to keep track of bit 15, so that when an overflow or underflow condition is present on POSCNT, the variable will toggle bit 15 ...
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... FRMDLY = 1), the Slave always acts as if the sync pulse precedes the first SPI data bit (FRMDLY = 0). The SPI will not function as described if Slave FRMDLY = 1. Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. Timer Gated ...
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... ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV instruction. Affected Silicon Revisions © 2010 Microchip Technology Inc. specifications #0 DS80447D-page 25 ...
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... T -40°C ≤ T Min Typ Max Units V — 0 — 0.8 SS 0.7 V — 5.5 DD 2.1 — 5.5 ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions V SMBus disabled V SMBus enabled V SMBus disabled V SMBus enabled © 2010 Microchip Technology Inc. ...
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... Added silicon issues 64 (UART), 65-66 (QEI) and 67 (I/O). Rev C Document (1/2010) Added silicon issue 68 (SPI). Rev D Document (6/2010) Updated silicon issue 4 (CPU). Added silicon issue 69 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). © 2010 Microchip Technology Inc. 2 C), 56-61 DS80447D-page 27 ...
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... NOTES: DS80447D-page 28 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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