DSPIC33FJ32GP204-E/ML Microchip Technology, DSPIC33FJ32GP204-E/ML Datasheet - Page 114
![16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ32GP204-E/ML
Manufacturer Part Number
DSPIC33FJ32GP204-E/ML
Description
16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
5.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ32GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- DSPIC33FJ32GP204-IPT PDF datasheet #5
- Current page: 114 of 284
- Download datasheet (4Mb)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
10.2
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
See
functionality.
10.3
The AD1PCFG and TRIS registers control the
operation of the analog-to-digital (A/D) port pins. The
port pins that are desired as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (V
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EXAMPLE 10-1:
EXAMPLE 10-2:
DS70290G-page 114
Incorrect:
BSET
BSET
Correct:
BSET
NOP
BSET
NOP
Preferred:
BSET
BSET
MOV
MOV
NOP
BTSS
“Pin
Open-Drain Configuration
Configuring Analog Port Pins
PORTB, #RB1
PORTB, #RB6
PORTB, #RB1
PORTB, #RB6
LATB, LATB1
LATB, LATB6
0xFF00, W0
W0, TRISBB
PORTB, #13
Diagrams” for the available pins and their
IH
specification.
DD
PORT WRITE/READ
PORT BIT OPERATIONS
(e.g., 5V) on any desired 5V
;Set PORTB<RB1> high
;Set PORTB<RB6> high
;Set PORTB<RB1> high
;Set PORTB<RB6> high
;Set PORTB<RB1> high
;Set PORTB<RB6> high
;Configure PORTB<15:8> as inputs
;and PORTB<7:0> as outputs
;Delay 1 cycle
;Next Instruction
OH
or V
OL
)
10.4
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP. Examples are shown in
and
ations, such as BSET PORTB, # RB0, which are single
cycle read-modify-write. All PORT bit operations, such
as MOV PORTB, W0 or BSET PORTB, # RBx, read
the pin and not the latch.
10.5
The input change notification function of the I/O ports
allows
dsPIC33FJ16GP304 devices to generate interrupt
requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 31 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Four control registers are associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
Note:
Example
I/O Port Write/Read Timing
Input Change Notification
the
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
10-2. This also applies to PORT bit oper-
dsPIC33FJ32GP202/204
© 2011 Microchip Technology Inc.
Example 10-1
and
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