DSPIC33FJ32MC202-E/MM Microchip Technology, DSPIC33FJ32MC202-E/MM Datasheet - Page 119

• Manufacturer Part Number: DSPIC33FJ32MC202-E/MM
• Description: 16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.0
All of the device pins (except V
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
FIGURE 10-1:
© 2011 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
I/O PORTS
Parallel I/O (PIO) Ports
of the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive refer-
ence source. To complement the infor-
mation in this data sheet, refer to Section
10. “I/O Ports” (DS70193) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available on Microchip
web site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Read Port
Read LAT
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR Port
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Output Enable
Peripheral Output Data
Peripheral Input Data
Peripheral Module Enable
Peripheral Module
PIO Module
DD
TRIS Latch
Data Latch
D
D
CK
CK
, V
SS
Q
Q
, MCLR and
in
Output Multiplexers
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin.
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
1
0
1
0
Output Enable
Output Data
Input Data
I/O
I/O Pin
DS70283H-page 119
Figure 10-1
shows