EP1S30F1020C5N Altera, EP1S30F1020C5N Datasheet - Page 95
EP1S30F1020C5N
Manufacturer Part Number
EP1S30F1020C5N
Description
Stratix
Manufacturer
Altera
Datasheet
1.EP1S30F1020C5N.pdf
(276 pages)
Specifications of EP1S30F1020C5N
Family Name
Stratix
Number Of Logic Blocks/elements
32470
# I/os (max)
726
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
32470
Ram Bits
3317184
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S30F1020C5N
Manufacturer:
ALTERA
Quantity:
455
Part Number:
EP1S30F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
Altera Corporation
July 2005
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKL[7:0]
You can use the Quartus II software to control whether a clock input pin
is either global, regional, or fast regional. The Quartus II software
automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix devices provide robust clock management and synthesis using up
to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover, spread
spectrum clocking, programmable bandwidth, phase and delay control,
and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you
with complete control of your clocks and system timing. The fast PLLs
8
IO_CLKB[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKJ[7:0]
8
IO_CLKD[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
Stratix Device Handbook, Volume 1
8
IO_CLKI[7:0]
8
Stratix Architecture
8
8
8
8
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
I/O Clock Regions
2–81
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