EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 31
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Altera Corporation
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
Clock A
APEX 20K Programmable Logic Device Family Data Sheet
ESB
ESB
ESB
Address Decoder
address_a[]
data_a[]
we_a
clkena_a
Figure
Port A
19.
address_b[]
clkena_b
Port B
data_b[]
we_b
to System Logic
Clock B
31
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