EP20K100QC208-1 Altera, EP20K100QC208-1 Datasheet - Page 38
EP20K100QC208-1
Manufacturer Part Number
EP20K100QC208-1
Description
APEX 20K
Manufacturer
Altera
Datasheet
1.EP20K100QC208-1.pdf
(117 pages)
Specifications of EP20K100QC208-1
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
159
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
2.5V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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APEX 20K Programmable Logic Device Family Data Sheet
38
Table 10
options in the Quartus II software.
The Quartus II software compiler can program these delays automatically
to minimize setup time while providing a zero hold time.
how fast bidirectional I/Os are implemented in APEX 20K devices.
The register in the APEX 20K IOE can be programmed to power-up high
or low after configuration is complete. If it is programmed to power-up
low, an asynchronous clear can control the register. If it is programmed to
power-up high, the register cannot be asynchronously cleared or preset.
This feature is useful for cases where the APEX 20K device controls an
active-low input or another device; it prevents inadvertent activation of
the input upon power-up.
Input pin to core delay
Input pin to input register delay
Core to output register delay
Output register t
Table 10. APEX 20K Programmable Delay Chains
Programmable Delays
describes the APEX 20K programmable delays and their logic
CO
delay
Decrease input delay to internal cells
Decrease input delay to input register
Decrease input delay to output register
Increase delay to output pin
Quartus II Logic Option
Altera Corporation
Figure 25
shows
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