EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 346
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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9
TXCtl
9-44
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Chip Reset:
When the host changes the destination filter, it is possible that a frame will be missed while
SerRxON is clear.
Note: It may become necessary for the host to change the destination address filter criteria and
30
14
1. Clear SerRxON (RXCtl) to prevent an additional received frame while the filters are
2. Modify the destination filter bits in this register.
3. Modify the Logical Address Filter, if necessary.
4. Modify the Individual Address Filter, if necessary.
5. Set SerRxON to re-enable the receiver.
being changed.
NOT go through a controller reset. This can be done. The host should:
29
13
28
12
IAHA:
IA3:
IA2:
IA1:
IA0:
0x8001_0004 - Read/Write
0x0000_0000
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Individual Address Hash Accept. When set, received
frame are accepted when the DA is an Individual Address
(first bit of DA = 0), that is accepted by the hash table. See
Descriptor Processor Transmit Registers.
Individual Accept 3. When set, received frames are
accepted which the DA matches the Individual Address 3
Register.
Individual Accept 2. When set, received frames are
accepted which the DA matches the Individual Address 2
Register.
Individual Accept 1. When set, received frames are
accepted which the DA matches the Individual Address 1
Register.
Individual Accept 0. When set, received frames are
accepted which the DA matches the Individual Address 0
Register.
24
8
RSVD
DefDis
23
7
MBE
22
6
ICRC
21
5
TxPD
20
4
OColl
19
3
SP
18
2
PB
17
1
DS785UM1
STxON
16
0
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