EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 476
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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11
USBCfgCtrl
11-36
Universal Serial Bus Host Controller
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
OCIC:
PRSC:
0x8002_0080 - Read/Write
0x0000_0000
Used to implement some input signals to USB host controller for configuration
through software.
RSVD:
TPOC:
TRCS:
27
11
RSVD
26
10
Copyright 2007 Cirrus Logic
25
9
PortOverCurrentIndicatorChange. This bit is valid only if
overcurrent conditions are reported on a per-port basis.
This bit is set when Root Hub changes the
PortOverCurrentIndicator bit. The HCD writes a “1” to
clear this bit. Writing a “0” has no effect.
0 = no change in PortOverCurrentIndicator
1 = PortOverCurrentIndicator has changed
PortResetStatusChange. This bit is set at the end of the
10 ms port reset signal. The HCD writes a “1” to clear this
bit. Writing a “0” has no effect.
0 = port reset is not complete
1 = port reset is complete
Reserved. Unknown During Read.
When asserted by software, the corresponding port will
enter DISCONNECT state. These bits must be cleared
before the ports can be reused.
Inverted internally and sent out as APP_CntSelN signal to
uhostc_top. Internally known as TicRegCntSel.
APP_CntSelN is used for selecting the counter value for
either simulation or real-time for the 1 ms frame duration
used internally. It should be usually set to “0”. Setting it to
“1” will cause the internal counter count to be a partial full
count.
24
8
RSVD
23
7
22
6
21
5
TRCS
20
4
19
3
TPOC
18
2
17
1
DS785UM1
RSVD
16
0
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