EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 528
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
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14
14-6
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14.2.2.1 Error Bits
14.2.2.2 Disabling the FIFOs
14.2.2.3 System/diagnostic Loopback Testing
14.2.2.4 UART Character Frame
Three error bits are stored in bits [10:8] of the receive FIFO, and are associated with a
particular character. See
error but it is not associated with a particular character in the receive FIFO. The overrun error
is set when the FIFO is full and the next character has been completely received in the shift
register. The data in the shift register is overwritten but it is not written into the FIFO.
Additionally, it is possible to disable the FIFOs. In this case, the transmit and receive sides of
the UART have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set
when a word has been received and the previous one was not yet read. In this
implementation, the FIFOs are not physically disabled, but the flags are manipulated to give
the illusion of a 1-byte register.
It is possible to perform loopback testing for UART data by setting the Loop Back Enable
(LBE) bit to 1 in the control register UARTxCtrl (bit 7).
Data transmitted on UARTTXD output will be received on the UARTRXD input.
The UART character frame is shown in
FIFO bit
7:0
10
9
8
Table
Table 14-1. Receive FIFO Bit Functions
Figure 14-2. UART Character Frame
Figure 14-3. UART Character Frame
Copyright 2007 Cirrus Logic
14-1. There is an additional error which indicates an overrun
Figure
14-2:
Received data
Framing error
Break error
Parity error
Function
DS785UM1
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