EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 590
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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16
16-14
UART3 With HDLC Encoder
EP93xx User’s Guide
RXENC:
SYNC:
TFCEN:
TABEN:
RFCEN:
RILEN:
RFLEN:
RTOEN:
FLAG:
CRCN:
Copyright 2007 Cirrus Logic
Receive Encoding method.
1 - Use Manchester bit encoding.
0 - Use NRZ bit encoding.
This bit has no effect unless synchronous HDLC is
enabled.
Synchronous / Asynchronous HDLC Enable.
0 - Select asynchronous HDLC for TX and RX.
1 - Select synchronous HDLC for TX and RX.
Transmit Frame Complete Interrupt Enable.
0 - TFC interrupt will not occur.
1 - TFC interrupt will occur whenever TFC bit is set.
Transmit Frame Abort Interrupt Enable.
0 - TAB interrupt will not occur.
1 - TAB interrupt will occur whenever TAB bit is set.
Receive Frame Complete Interrupt Enable.
0 - RFC interrupt will not occur.
1 - RFC interrupt will occur whenever RAB bit or EOF bit is
set.
Receive Information Lost Interrupt Enable.
0 - RIL interrupt will not occur.
1 - RIL interrupt will occur whenever RIL bit is set.
Receive Frame Lost Interrupt Enable.
0 - RFL interrupt will not occur.
1 - RFL interrupt will occur whenever RFL bit is set.
Receiver Time Out Interrupt Enable.
0 - RTO interrupt will not occur.
1 - RTO interrupt will occur whenever RTO bit is set.
Minimum number of opening and closing flags for HDLC
TX. The minimum number of flags between packets is this
4-bit value plus one. Hence, 0000b forces at least one
opening flag and one closing flag for each packet, and
1111b forces at least 16 opening and closing flags. The
closing flags of one packet may also be the opening flags
of the next one if the transmit line does not go idle in
between. Note that HDLC RX does not count flags; only
one is necessary (or three in Manchester mode).
CRC polarity control.
0 - CRC transmitted not-inverted.
1 - CRC transmitted inverted.
DS785UM1
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