EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 708
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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22
AC97IM
AC97EOI
22-20
AC’97 Controller
EP93xx User’s Guide
31
15
31
15
Address:
Definition:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
0x8088_0094 - Read/Write
Controller Interrupt Enable Register. The AC’97 Controller interrupt enable
register is a read/write register that controls the interrupt enables for the
interrupts outside the FIFO channels.
Bit Descriptions:
RSVD:
SLOT2TXCOMPLETE:If this bit is set to “1”, the SLOT2TXCOMPLETE
CODECREADY:
WINT:
GPIOINT:
GPIOTXCOMPLETE:If this bit is set to “1”, the GPIOTXCOMPLETE interrupt
SLOT2RXVALID: If this bit is set to “1”, SLOT2RXVALID interrupt is enabled.
SLOT1TXCOMPLETE:If this bit is set to “1”, SLOT1TXCOMPLETE interrupt is
0x8088_0098 - Write Only
RSVD
27
11
27
11
26
10
26
10
25
9
Copyright 2007 Cirrus Logic
25
9
RSVD
Reserved. Unknown During Read.
If this bit is set to “1”, the Codec Ready Interrupt is
If this bit is set to “1”, the Wake-up Interrupt is enabled.
If this bit is set to “1”, the GPIO interrupt is enabled.
24
8
24
8
interrupt is enabled.
enabled.
is enabled.
enabled.
23
7
RSVD
23
7
COMPLETE
SLOT2TX
22
6
22
6
CODEC
READY
21
5
21
5
WINT
20
4
20
4
GPIO
INT
19
3
19
3
COMPLETE
GPIOTX
18
18
2
2
CODECREADY
SLOT2RX
VALID
17
17
1
1
DS785UM1
COMPLETE
SLOT1TX
WINT
16
0
16
0
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