EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 786
EP9307-CRZR
Manufacturer Part Number
EP9307-CRZR
Description
IC Universal Platform ARM9 SOC Prcessor
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9307-CRZR
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-LFBGA
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
Q5809834A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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27
IDEUDMADataIn
IDEUDMASts
27-16
IDE Interface
EP93xx User’s Guide
31
15
31
15
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
30
14
30
14
RSVD
RSVD
29
13
29
13
28
12
28
12
addressed and written by the DMA controller. A write by the host during UDMA
data-out operation will erroneously interfere with the UDMA state machine.
Any read will return zero.
IDEDD:
0x800A_0024 - Read Only (should be read by the DMA controller only)
0x0000_0000
In UDMA data-in operations, this register contains the data at the head of the
input buffer to be transferred by the DMA controller. The data is read from this
register by the DMA controller. This register should only be addressed and
read by the DMA controller. A read by the host during UDMA data-in operation
will erroneously interfere with the UDMA state machine. Any write is ignored.
IDEDD:
0x800A_0028 - Read Only
0x0000_0000
27
27
11
11
DSDD
N4X
26
10
26
10
Copyright 2007 Cirrus Logic
DMARQ
NDI
25
25
9
9
IDE output data at the tail of the output buffer in UDMA
mode.
IDE input data at the head of the input buffer in UDMA
mode.
DDOE
NDO
24
24
8
8
IDEDD
IDEDD
DM
23
23
7
7
STOP
22
22
6
6
RSVD
HSHD
21
21
5
5
20
20
4
4
DA
19
19
3
3
SBUSY
18
18
2
2
INTide
CS1n
17
17
1
1
DS785UM1
DMAide
CS0n
16
16
0
0
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