EVAL-AD5263EBZ Analog Devices Inc, EVAL-AD5263EBZ Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD5263EBZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5263EBZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5263
• Primary Attributes: 4 Channel, 256 Position
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5263
4.
A repeated write function gives the user flexibility to update
the RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output updates on each successive byte.
If different instructions are needed, the write/read mode has to
start again with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5263 features additional programmable logic outputs,
O1 and O2, which can be used to drive a digital load, analog
switches, and logic gates. O1 and O2 default to Logic 0. The
voltage level can swing from GND to V
and O2 can be programmed in Frame 2 under write mode (see
Figure 43). These logic outputs have adequate current driving
capability to sink/source milliamperes of load.
Users can also activate O1 and O2 in three different ways
without affecting the wiper settings. They may do the following:
•
•
•
SELF-CONTAINED SHUTDOWN FUNCTION
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte. In
addition, shutdown can even be implemented with the device’s
digital output, as shown in
device is shut down during power-up, but users are allowed to
program the device. Thus, when O1 is programmed high, the
device exits from the shutdown mode and responds to the new
setting. This self-contained shutdown function allows absolute
shutdown during power-up, which is crucial in hazardous
environments, without adding extra components.
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 43). In read mode, the master issues a
no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the tenth clock pulse, which goes high to
establish a STOP condition (see Figure 44).
START, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, STOP.
Complete the write cycle with STOP, then START, slave
address byte, acknowledge, instruction byte with O1 and
O2 specified, acknowledge, STOP.
Do not complete the write cycle by not issuing the STOP,
then START, slave address byte, acknowledge, instruction
byte with O1 and O2 specified, acknowledge, STOP.
Figure 48
. In this configuration, the
L
. The logic states of O1
Rev. B | Page 20 of 28
MULTIPLE DEVICES ON ONE BUS
Figure 49 shows four AD5263 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 and AD1 pins are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain, pull-
downs in a fully I
LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION
The digital potentiometer is popular in laser diode driver and
certain telecommunication equipment level-setting applications.
These applications are sometimes operated between ground and
some negative supply voltage so that the systems can be biased at
ground to avoid large bypass capacitors that may significantly
impede the ac performance. Like most digital potentiometers, the
AD5263 can be configured with a negative supply (see Figure 50).
MASTER
SDA SCL
AD0
AD5263
AD1
Figure 49. Multiple AD5263 Devices on One I
LEVEL SHIFTED
LEVEL SHIFTED
R
Figure 48. Shutdown by Internal Logic Output
P
Figure 50. Biased at Negative Voltage
R
2
PULL-DOWN
C-compatible interface.
5V
R
P
–5V
SDA SCL
AD5263
AD0
AD1
+5V
O1
SHDN
SDA
SCL
5V
GND
V
V
SDA
SCL
AD5263
DD
SS
AD5263
SDA SCL
AD5263
AD0
AD1
5V
2
C Bus
SDA SCL
AD5263
AD0
AD1
SDA
SCL