EVAL-AD7841EBZ Analog Devices Inc, EVAL-AD7841EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-AD7841EBZ
• Description: Evaluation Board I.c.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7841EBZ

• Number Of Dac's: 8
• Number Of Bits: 14
• Outputs And Type: 8, Single Ended
• Sampling Rate (per Second): 32k
• Data Interface: Parallel
• Settling Time: 31µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. B
Pin
No.
1
2, 44, 43,
41, 37, 35,
34, 32
3, 4
5, 38
6
7
8, 9, 10
11
12
13
14
15–28
29
30, 31
33
36
39
40
42
Mnemonic
DUTGND_AB
V
V
V
V
LDAC
A2, A1, A0
CS
WR
V
GND
DB0 . . DB12
CLR
V
DUTGND_GH
DUTGND_EF
V
V
DUTGND_CD
OUT
REF
DD
SS
CC
REF
REF
REF
(–)AB, V
(+)GH, V
(+)CDEF
(–)CDEF
A . . V
OUT
REF
REF
H
(+)AB
(–)GH
Description
Device Sense Ground for DACs A and B. V
applied to this pin.
DAC Outputs.
Reference Inputs for DACs A and B. These reference voltages are referred to GND.
Positive Analog Power Supply; +15 V ± 10% for specified performance.
Negative Analog Power Supply; –15 V ± 10% for specified performance.
Load DAC Logic Input (active low). When this logic input is taken low the contents of the
registers are transferred to their respective DAC registers. LDAC can be tied permanently
low enabling the outputs to be updated on the rising edge of WR.
Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Level-Triggered Write Input (active low), used in conjunction with CS to write data to the
AD7841 data registers. Data is latched into the selected input register on the rising edge
of WR.
Logic Power Supply; 5 V ± 5%.
Ground.
Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to
DB13 where DB13 is the MSB and DB0 is the LSB.
Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the CLR pin is taken
low. When CLR is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
Reference Inputs for DACs G and H. These reference voltages are referred to GND.
Device Sense Ground for DACs G and H. V
applied to this pin.
Device Sense Ground for DACs E and F. V
applied to this pin.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Device Sense Ground for DACs C and D. V
applied to this pin.
PIN FUNCTION DESCRIPTIONS
OUT
OUT
OUT
OUT
E and V
A and V
C and V
G and V
OUT
OUT
OUT
OUT
F are referenced to the voltage
B are referenced to the voltage
D are referenced to the voltage
H are referenced to the voltage
AD7841