KSZ8851-16MLL TR Micrel Inc, KSZ8851-16MLL TR Datasheet
KSZ8851-16MLL TR
Specifications of KSZ8851-16MLL TR
Related parts for KSZ8851-16MLL TR
KSZ8851-16MLL TR Summary of contents
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... TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface. The KSZ8851-16MLL is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature-grade version of the KSZ8851-16MLL, the KSZ8851-16MLLI ...
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... Low-power CMOS design • Commercial Temperature Range: 0 • Industrial Temperature Range: –40 • Flexible package options available in 48-pin (7mm x 7mm) LQFP KSZ8851-16MLL or 128-pin PQFP KSZ8851-16/32MQL August 2009 Additional Features In addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLL offers: • ...
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... Micrel, Inc. Ordering Information Part Number Temperature Range KSZ8851-16MLL KSZ8851-16MLLI KSZ8851-16MLL-Eval Evaluation Board for the KSZ8851-16MLL Revision History Revision Date 1.0 06/30/2008 1.1 2/13/2009 2.0 8/31/2009 August 2009 – +85 C Summary of Changes First released Information. Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table content and description. Change revision ID from “ ...
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... Address Filtering Function ....................................................................................................................... 22 Clock Generator....................................................................................................................................... 23 Bus Interface Unit (BIU)......................................................................................................................... 23 Supported Transfers ................................................................................................................................ 23 Physical Data Bus Size ............................................................................................................................ 23 Little and Big Endian Support................................................................................................................... 23 Asynchronous Interface ........................................................................................................................... 24 BIU Summation........................................................................................................................................ 24 Queue Management Unit (QMU) ........................................................................................................... 24 Transmit Queue (TXQ) Frame Format ..................................................................................................... 24 Frame Transmitting Path Operation in TXQ ............................................................................................. 26 August 2009 4 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Micrel, Inc. Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL.......................................... 26 Receive Queue (RXQ) Frame Format...................................................................................................... 29 Frame Receiving Path Operation in RXQ................................................................................................. 29 Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor........................................... 30 EEPROM Interface ................................................................................................................................. 31 Loopback Support ................................................................................................................................. 32 Near-end (Remote) Loopback.................................................................................................................. 32 Far-end (Local) Loopback ........................................................................................................................ 32 CPU Interface I/O Registers .......................................................................................................................... 33 I/O Registers ...
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... Indirect Access Data Low Register (0xD0 – 0xD1): IADLR ...................................................................... 59 Indirect Access Data High Register (0xD2 – 0xD3): IADHR ..................................................................... 59 Power Management Event Control Register (0xD4 – 0xD5): PMECR ...................................................... 59 Go-Sleep & Wake-Up Time Register (0xD6 – 0xD7): GSWUTR .............................................................. 61 PHY Reset Register (0xD8 – 0xD9): PHYRR........................................................................................... 61 August 2009 6 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Additional MIB Information ....................................................................................................................... 69 (1) Absolute Maximum Ratings (2) Operating Ratings ....................................................................................................................................... 70 (4, 5) Electrical Characteristics Timing Specifications.................................................................................................................................... 72 Asynchronous Read and Write Timing ..................................................................................................... 72 Auto Negotiation Timing........................................................................................................................... 73 Reset Timing............................................................................................................................................ 74 EEPROM Timing...................................................................................................................................... 75 Selection of Isolation Transformers............................................................................................................. 76 Selection of Reference Crystal ..................................................................................................................... 76 Package Information ..................................................................................................................................... 77 Acronyms and Glossary ............................................................................................................................... 78 August 2009 ....................................................................................................................... 70 ......................................................................................................................... 70 7 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Figure 3. Typical Straight Cable Connection ........................................................................................................................ 18 Figure 4. Typical Crossover Cable Connection .................................................................................................................... 19 Figure 5. Auto Negotiation and Parallel Operation ............................................................................................................... 20 Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections..................................................................................... 24 Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram .................................................................................... 27 Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram ................................................................................... 28 Figure 9. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram .................................................................... 30 Figure 10 ...
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... Table 7. Transmit Byte Count Format.................................................................................................................................. 25 Table 8. Registers Setting for Transmit Function Block....................................................................................................... 26 Table 9. Frame Format for Receive Queue ......................................................................................................................... 29 Table 10. Registers Setting for Receive Function Block...................................................................................................... 29 Table 11. KSZ8851-16MLL EEPROM Format..................................................................................................................... 31 Table 12. Format of MIB Counters....................................................................................................................................... 68 Table 13. Port 1 MIB Counters Indirect Memory Offsets ..................................................................................................... 69 Table 14. Electrical Characteristics...................................................................................................................................... 71 Table 15 ...
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... Micrel, Inc. Pin Configuration August 2009 Figure 2. 48-Pin LQFP 10 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Power Management Event (default active low asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low power mode. Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4 ...
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... Shared Data Bus bit 10. Data D10 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode. Shared Data Bus bit 9. Data D9 access when CMD=0. Don’t care when CMD=1. This pin must be tied to GND in 8-bit bus mode. Digital ground 12 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... NC or Pull-down (default) = Little Endian This pin value is latched into register CCR, bit 10. When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode. 13 KSZ8851-16MLL/MLLI Pin Function M9999-083109-2.0 ...
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... The energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present connected to a powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can automatically power up to normal power state in energy detect mode ...
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... PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from power saving mode. ...
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... If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and takes no further action. If the KSZ8851-16MLL controller detects the data sequence, however, it then alerts the PC’s power management circuitry (assert the PME pin) to wake up the system. ...
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... The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs for the KSZ8851-16MLL device. This feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port ...
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... RD- Table 2. MDI/MDI-X Pin Definitions 10/100 Ethernet Media Dependent Interface 1 Transmit Pair 2 Straight 3 Cable 4 Receive Pair Modular Connector (RJ-45) NIC Figure 3. Typical Straight Cable Connection 18 KSZ8851-16MLL/MLLI MDI-X Signals 1 RD+ 2 RD- 3 TD+ 6 TD- 10/100 Ethernet Media Dependent Interface 1 Receive Pair Transmit Pair ...
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... If auto negotiation is not supported or the link partner to the KSZ8851-16MLL is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Set Link Mode ® LinkMD Cable Diagnostics ® The KSZ8851-16MLL LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of ± ...
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... If P1SCLMD[14:13]=11, this indicates an invalid test, and occurs when the KSZ8851-16MLL is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8851-16MLL to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... Perfect with Physical 11 1 address passed Notes: 1. Bit 0 (RX Enable), Bit 5 (RX Unicast Enable) and Bit 6 (RX Multicast Enable) must set RXCR1 register. 2. The KSZ8851-16MLL will discard frame with SA same as the MAC address if bit[0] is set in RXCR2 register. August 2009 RX Physical RX Multicast RX Inverse ...
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... Shared Data bus SD[15:0] for Address, Data and Byte Enable, Command (CMD), Chip Select Enable (CSN), Read (RDN), Write (WRN) and Interrupt (INTRN). Physical Data Bus Size The BIU supports an 8-bit or 16-bit host standard data bus. Depending on the size of the physical data bus, the KSZ8851- 16MLL can support 8-bit or 16-bit data transfers. For example, For a 16-bit data bus mode, the KSZ8851-16MLL allows an 8-bit and 16-bit data transfer ...
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... For asynchronous transfers, the asynchronous interface uses RDN (read) and WRN (write) signal strobes for data latching. The host utilizes the rising edge of RDN to latch read data and the KSZ8851-16MLL will use falling edge of WRN to latch write data. All asynchronous transfers are either single-data or burst-data transfers. Byte or word data bus access (transfers) is supported ...
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... The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The KSZ8851-16MLL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the KSZ8851-16MLL treated transparently as data both for transmit operations. ...
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... Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to be cleared before setting up another new TX frame. When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR register) to CPU TXQCR[1](0x80) when TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR (0x9E) register ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until whole Write an 0?to RXQCR[3] reg to end Write an 1?to TXQCR[0] reg to issue a transmit command (manual-enqueue) to the TXQ ...
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... TXQ write access, then Host starts write transmit data (control word, byte count and pkt data) to TXQ memory. This is moving transmit data from Host to KSZ8851M TXQ memory until all Write an 0?to RXQCR[3] reg to end Option to read ISR[14] reg, it indicates that the TXQ has completed to transmit ...
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... RX interrupt in ISR[13] and indicate the status in RXQCR[12]. RXDBCTR[15:0](0x8E) To program received data byte count value. When the number of received bytes in RXQ exceeds this threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX interrupt in ISR[13] and indicate the status in RXQCR[11]. IER[13](0x90) Set bit 13 to enable receive interrupt in Interrupt Enable Register ...
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... Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor The software driver receives data packet frames from the KSZ8851-16MLL device either as a result of polling or an interrupt based service. When an interrupt is received, the OS invokes the interrupt service routine that is in the interrupt vector table ...
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... EEPROM Interface It is optional in the KSZ8851-16MLL to use an external EEPROM. The EED_IO (pin 9) must be pulled high to use external EEPROM otherwise this pin pulled low or floating without EEPROM. An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such as the host MAC address ...
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... PHY port will be set to 100BASE-TX full-duplex mode. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at PHY port 1 of the KSZ8851-16MLL. The loopback path starts at the PHY port’s receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXP1/TXM1) ...
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... Micrel, Inc. CPU Interface I/O Registers The KSZ8851-16MLL provides an SRAM-like asynchronous bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is used for configuring operational settings, reading or writing control, status information, and transferring packets. The KSZ8851- 16MLL can be programmed to interface with either Big-Endian or Little-Endian processor ...
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... MBIR 0x1010 Memory BIST Info Register [15:8] Global Reset Register [7:0] GRR 0x0000 Global Reset Register [15:8] Reserved Don’t care None Wakeup Frame Control Register [7:0] WFCR 0x0000 Wakeup Frame Control Register [15:8] Reserved Don’t care 34 KSZ8851-16MLL/MLLI Description M9999-083109-2.0 ...
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... Wakeup Frame 2 Byte Mask 1 Register [15:8] Wakeup Frame 2 Byte Mask 2 Register [7:0] WF2BM2 0x0000 Wakeup Frame 2 Byte Mask 2 Register [15:8] Wakeup Frame 2 Byte Mask 3 Register [7:0] 0x0000 WF2BM3 Wakeup Frame 2 Byte Mask 3 Register [15:8] Reserved Don’t care None 35 KSZ8851-16MLL/MLLI Description M9999-083109-2.0 ...
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... RXFDPR 0x0000 RX Frame Data Pointer Register [15:8] Reserved Don’t care None RX Duration Timer Threshold Register [7:0] RXDTTR 0x0000 RX Duration Timer Threshold Register [15:8] RX Data Byte Count Threshold Register [7:0] RXDBCTR 0x0000 RX Data Byte Count Threshold Register [15:8] 36 KSZ8851-16MLL/MLLI Description M9999-083109-2.0 ...
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... Flow Control High Watermark Register [7:0] FCHWR 0x0300 Flow Control High Watermark Register [15:8] Flow Control Overrun Watermark Register [7:0] FCOWR 0x0040 Flow Control Overrun Watermark Register [15:8] Reserved Don’t care None Reserved Don’t care None Reserved Don’t care None 37 KSZ8851-16MLL/MLLI Description M9999-083109-2.0 ...
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... PHY 1 PHY ID High Register [7:0] PHY1IHR 0x0022 PHY 1 PHY ID High Register [15:8] PHY 1 Auto-Negotiation Advertisement Register [7:0] P1ANAR 0x05E1 PHY 1 Auto-Negotiation Advertisement Register [15:8] PHY 1 Auto-Negotiation Link Partner Ability Register [7:0] P1ANLPR 0x0001 PHY 1 Auto-Negotiation Link Partner Ability Register [15:8] 38 KSZ8851-16MLL/MLLI Description M9999-083109-2.0 ...
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... Port 1 PHY Special Control/Status, LinkMD Port 1 Control Register [7:0] P1CR 0x00FF Port 1 Control Register [15:8] Port 1 Status Register [7:0] P1SR 0x8080 Port 1 Status Register [15:8] Reserved Don’t care None Reserved Don’t care None 39 KSZ8851-16MLL/MLLI Description ® [7:0] ® [15:8] M9999-083109-2.0 ...
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... Not in 16-bit bus mode operation 16-bit bus mode operation. Reserved. Shared data bus mode for data and address 0: Data and address bus are seperated. 1: Data and address bus are shared. Reserved. Reserved. 48-Pin Chip Package To indicate chip package is 48-pin. 0: No, 1: Yes. Reserved. 40 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... On-Chip Bus Control Register (0x20 – 0x21): OBCR This register controls the on-chip bus clock speed for the KSZ8851-16MLL. The default of the on-chip bus clock speed is 125MHz. When the external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance ...
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... EEPROM is not used, the software programs the host MAC address EEPROM is used in the design, the chip host MAC address is loaded from the EEPROM immediately after reset. The KSZ8851-16MLL allows the software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is set ...
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... When reset, the Wake up frame 1 pattern detection is disabled. WF0E Wake up Frame 0 Enable When set, it enables the Wake up frame 0 pattern detection. When reset, the Wake up frame 0 pattern detection is disabled. Description WF0CRC0 Wake up Frame 0 CRC (lower 16 bits) The expected CRC value of a Wake up frame 0 pattern. 43 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... The next 16 bytes mask covering bytes Wake-up frame 0 pattern. Description WF0BM3 Wake-up Frame 0 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 0 pattern. Description WF1CRC0 Wake-up frame 1 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 1 pattern. 44 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... The next 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF1BM3 Wake-up frame 1 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 1 pattern. Description WF2CRC0 Wake-up frame 2 CRC (lower 16 bits). The expected CRC value of a Wake-up frame 2 pattern. 45 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Wake-up frame 2 Byte Mask 2. The next 16 bytes mask covering bytes Wake-up frame 2 pattern. Description WF2BM3 Wake-up frame 2 Byte Mask 3. The last 16 bytes mask covering bytes Wake-up frame 2 pattern. Description WF3CRC0 Wake-up frame 3 CRC (lower 16 bits). The expected CRC value of a Wake up frame 3 pattern. 46 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... WF3BM3 Wake up Frame 3 Byte Mask 3. The last 16 bytes mask covering bytes Wake up frame 3 pattern. Description Reserved. TCGICMP Transmit Checksum Generation for ICMP When this bit is set, The KSZ8851-16MLL is enabled to transmit ICMP frame (only for non-fragment frame) checksum generation. Reserved. 47 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... TXFCE Transmit Flow Control Enable When this bit is set and the KSZ8851-16MLL is in full-duplex mode, flow control is enabled. The KSZ8851-16MLL transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold level that will cause the buffer to overflow. When this bit is set and the KSZ8851-16MLL is in half-duplex mode, back-pressure flow control is enabled ...
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... Any received TCP frames with incorrect checksum will be discarded. RXIPFCC Receive IP Frame Checksum Check Enable When this bit is set, the KSZ8851 will check for correct IP header checksum for incoming IP frames. Any received IP frames with incorrect checksum will be discarded. RXPAFMA Receive Physical Address Filtering with MAC Address Enable ...
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... Description Reserved. IUFFP IPV4/IPV6/UDP Fragment Frame Pass When this bit is set, the KSZ8851-16MLL will pass the checksum check at receive side for IPv4/IPv6 UDP frame with fragment extension header. When this bit is cleared, the KSZ8851-16MLL will perform checksum operation based on configuration and doesn’t care whether it’s a fragment frame or not. ...
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... RXTCPFCS Receive TCP Frame Checksum Status When this bit is set, the KSZ8851 received TCP frame checksum field is incorrect. RXUDPFCS Receive UDP Frame Checksum Status When this bit is set, the KSZ8851 received UDP frame checksum field is incorrect. Reserved RXBF Receive Broadcast Frame When this bit is set, it indicates that this frame has a broadcast address ...
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... RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register (0x8C, RXDTT). RXDBCTE RX Data Byte Count Threshold Enable When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) 52 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Byte Count Threshold Register (0x8E, RXDBCT). RXFCTE RX Frame Count Threshold Enable When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C, RXFCT). ...
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... To program received frame duration timer threshold value in 1us interval. The maximum value is 0xCFFF. When bit 7 set RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in ISR) after the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register. ...
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... When this bit is set, it indicates that the link status has changed from link up to link down, or link down to link up. This edge-triggered interrupt status is cleared by writing 1 to this bit. TXIS Transmit Interrupt Status When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the 55 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... To indicate the total received frames in RXQ frame buffer when receive interrupt (bit13=1 in ISR) occurred and write “1” to clear this bit 13 in ISR. The host CPU can start to read the updated receive frame header information in RXFHSR/RXFHBCR registers after read this RX frame count register. 56 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Multicast table register 3. August 2009 RXFCT Receive Frame Count Threshold To program received frame count threshold value. When bit 5 set RXQCR register, the KSZ8851-16MLL will set RX interrupt (bit 13 in ISR) when the number of received frames in RXQ buffer exceeds the threshold set in this register. Description ...
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... FCLWC Flow Control Overrun Watermark Configuration These bits are used to define the QMU RX queue overrun watermark configuration double words count and default is 256 Bytes available buffer space out of 12 Kbyte. Description Family ID Chip family ID Chip ID 0x7 is assigned to KSZ8851-16MLL Revision ID Reserved 58 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... This register contains the indirect data (high word) for MIB counter. Bit Default R/W 15-0 0x0000 RW Power Management Event Control Register (0xD4 – 0xD5): PMECR This register is used to control the KSZ8851-16MLL power management event, capabilities and status. Bit Default Value R August 2009 Description Reserved ...
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... This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1. Wake-Up Event Indication These four bits are used to indicate the KSZ8851-16MLL wake-up event status as below: 0000: No wake-up event. 0001: Wake-up from energy event detected. (Bit 2 also set ISR register) 0010: Wake-up from link up event detected ...
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... Tx -> PHY -> host Rx, see Figure 10 normal operation Force 100 1 = force 100Mbps disabled (bit 12 force 10Mbps disabled (bit 12) AN Enable 1 = auto-negotiation enabled auto-negotiation disabled. Reserved Restart restart auto-negotiation normal operation. 61 KSZ8851-16MLL/MLLI Bit is same as: Bit 6 in P1CR Bit 7 in P1CR Bit 13 in P1CR M9999-083109-2.0 ...
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... Reserved. Preamble suppressed Not supported. AN Complete 1 = auto-negotiation complete auto-negotiation not completed. Reserved AN Capable 62 KSZ8851-16MLL/MLLI Bit is same as: Bit 5 in P1CR Bit 15 in P1SR Bit 9 in P1CR Bit 10 in P1CR Bit 14 in P1CR Bit 15 in P1CR Bit is same as: Bit 6 in P1SR ...
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... Adv 10 Full 1 = advertise 10 full-duplex capability not advertise 10 full-duplex capability. Adv 10 Half 1 = advertise 10 half-duplex capability not advertise 10 half-duplex capability. 63 KSZ8851-16MLL/MLLI Bit is same as: Bit 5 in P1SR Bit is same as: Bit 4 in P1CR Bit 3 in P1CR Bit 2 in P1CR Bit 1 in P1CR Bit 0 in P1CR M9999-083109-2 ...
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... It is self- cleared after the VCT test is done indicates the cable diagnostic test is completed and the status information is valid for read. 64 KSZ8851-16MLL/MLLI Bit is same as: Bit 4 in P1SR Bit 3 in P1SR Bit 2 in P1SR Bit 1 in P1SR Bit 0 in P1SR Bit is same as: M9999-083109-2 ...
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... AN is disabled (bit 7). Force Duplex 1 = force full duplex if ( disabled or ( enabled but failed force half duplex if ( disabled or ( enabled but failed. 65 KSZ8851-16MLL/MLLI Bit is same as: Bit 0 in P1MBCR Bit 1 in P1MBCR Bit 9 in P1MBCR Bit 3 in P1MBCR Bit 4 in P1MBCR Bit 12 in P1MBCR ...
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... Link Good 1= link good link not good. Partner flow control capability 1 = link partner flow control (pause) capable link partner not flow control (pause) capable. 66 KSZ8851-16MLL/MLLI Bit is same as: Bit 10 in P1ANAR Bit 8 in P1ANAR Bit 7 in P1ANAR Bit 6 in P1ANAR Bit 5 in P1ANAR ...
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... Partner 10BT half-duplex capability 1 = link partner 10BT half-duplex capable link partner not 10BT half-duplex capable. 67 KSZ8851-16MLL/MLLI Bit is same as: Bit 8 in P1ANLPR Bit 7 in P1ANLPR Bit 6 in P1ANLPR Bit 5 in P1ANLPR ...
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... Micrel, Inc. MIB (Management Information Base) Counters The KSZ8851-16MLL provides 32 MIB counters to monitor the port activity for network management. The MIB counters are formatted as shown below: Bit Name R/W 31-0 Counter RO values Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F. ...
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... Tx total collision, half duplex only A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision Table 13. Port 1 MIB Counters Indirect Memory Offsets 69 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Set Bit [1: PMECR register At low power state V = GND ~ VDD_IO -8mA 8mA OL /θ is under air velocity 0m/ KSZ8851-16MLL/MLLI (2) VDD_A3.3 .......................................... +3.1V to +3.5V VDD_IO (3.3V) ................................... +3.1V to +3.5V VDD_IO (2.5V) ............................... +2.35V to +2.65V VDD_IO (1.8V) ................................... +1.7V to +1. (3) Junction-to-Ambient (θ ) ..........................83.56°C/W JA Junction-to-Case (θ ) ...............................35.90°C/W JC Min Typ ...
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... Condition 100Ω termination on the diff. output 100Ω termination on the diff. output Peak-to-peak 5MHz square wave 100Ω termination on the differential output 100Ω termination on the differential output (Peak-to-peak) Table 14. Electrical Characteristics 71 KSZ8851-16MLL/MLLI Min Typ Max Units ±0.95 ±1. ...
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... WRN active to write data valid (bit12=1 in RXFDPR) RDN Read active time (low) t6 WRN Write active time (low) RDN Read inactive time (high) t7 WRN Write inactive time (high) August 2009 valid Figure 11. Asynchronous Cycle Parameter Table 15. Asynchronous Cycle Timing Parameters 72 KSZ8851-16MLL/MLLI valid t7 valid Min Typ Max Unit ...
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... August 2009 Figure 12. Auto Negotiation Timing Description FLP burst to FLP burst FLP burst width Clock/Data pulse width Clock pulse to data pulse Clock pulse to clock pulse Number of Clock/Data pulses per burst Table 16. Auto Negotiation Timing Parameters 73 KSZ8851-16MLL/MLLI Min Typ Max Unit 100 ns 55 ...
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... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8851-16MLL supply voltages (3.3V). The reset timing requirement is summarized in the Figure 13 and Table 17. Symbol sr Stable supply voltages to reset High ...
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... Micrel, Inc. EEPROM Timing Timing Parameter tcyc ts th August 2009 Figure 14. EEPROM Read Cycle Timing Diagram Description Min Clock cycle 0.8 (OBCR[1:0]=00 on-chip bus speed @ 125 MHz) Setup time 20 Hold time 20 Table 18. EEPROM Timing Parameters 75 KSZ8851-16MLL/MLLI Typ Max Unit μ M9999-083109-2 ...
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... Part Number Auto MDI-X H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Table 20. Qualified Single Port Magnetics Value 25 ± Table 21. Typical Reference Crystal Characteristics 76 KSZ8851-16MLL/MLLI Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes ...
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... Micrel, Inc. Package Information August 2009 Figure 15. 48-Pin (7mm x 7mm) LQFP 77 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... Large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. An Ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null-modem, or crossover, cable. MDI provides the standard interface to a particular media (copper or fiber) and is therefore 'media dependent.' 78 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...
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... A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. 79 KSZ8851-16MLL/MLLI M9999-083109-2.0 ...