MC74HC597ADG ON Semiconductor, MC74HC597ADG Datasheet - Page 5

• Manufacturer Part Number: MC74HC597ADG
• Description: IC SHIFT REGISTER 8BIT 16SOIC
• Manufacturer: ON Semiconductor

Specifications of MC74HC597ADG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

* Used to determine the no−load dynamic power consumption: P
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
input latch on the rising edge of the Latch Clock input.
S
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
AC ELECTRICAL CHARACTERISTICS
A
Parallel data inputs. Data on these inputs is stored in the
Serial data input. Data on this input is shifted into the shift
Shift register mode control. When a high level is applied
Symbol
(Pin 14)
t
t
t
t
f
t
t
t
t
t
C
PLH
PLH
PLH
TLH
C
max
PHL
PHL
PHL
PHL
THL
PD
in
,
,
,
,
Maximum Clock Frequency (50% Duty Cycle), Shift Clock
Maximum Propagation Delay, Latch Clock to Q
Maximum Propagation Delay, Shift Clock to Q
Maximum Propagation Delay, Reset to Q
Maximum Propagation Delay, Serial Shift/Parallel Load to Q
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)*
(Figures 4 and 10)
(Figures 3 and 10)
(Figures 4 and 10)
(Figures 5 and 10)
(Figures 6 and 10)
(Figures 3 and 10)
Parameter
(C
L
= 50 pF, Input t
H
PIN DESCRIPTIONS
http://onsemi.com
H
H
r
= t
D
5
f
= C
= 6 ns)
PD
Reset (Pin 10)
applied to this input resets the shift register to a low level,
but does not change the data in the input latch.
Shift Clock (Pin 11)
input shifts data on the Serial Data Input into the shift
register and data in stage H is shifted out Q
replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
the parallel data on inputs A−H into the input latch.
OUTPUT
Q
stage of the shift register.
H
H
Asynchronous, Active−low shift register reset. A low level
Serial shift register clock. A low−to−high transition on this
Latch clock. A low−to−high transition on this input loads
Serial data output. This pin is the output from the last
V
(Pin 9)
CC
2
f + I
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
V
V
CC
CC
.
– 55 to
25_C
Typical @ 25°C, V
175
100
160
160
160
10
15
30
50
40
30
90
30
25
90
30
25
90
30
25
75
27
15
13
10
Guaranteed Limit
v 85_C
225
110
200
130
200
130
200
130
14
28
45
50
40
40
30
40
30
40
30
95
32
19
16
10
40
9
CC
v 125_C
= 5.0 V
275
125
240
160
240
160
240
160
110
12
25
40
60
50
48
40
48
40
48
40
36
22
19
10
8
H
, being
MHz
Unit
ns
ns
ns
ns
ns
pF
pF