FDG6318PZ Fairchild Semiconductor, FDG6318PZ Datasheet - Page 2

• Manufacturer Part Number: FDG6318PZ
• Description: MOSFET P-CH DUAL 20V SC70-6
• Manufacturer: Fairchild Semiconductor

Specifications of FDG6318PZ

• Fet Type: 2 P-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 780 mOhm @ 500mA, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 500mA
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 1.62nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 85.4pF @ 10V
• Power - Max: 300mW
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Configuration: Dual
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.78 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 1.1 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 12 V
• Continuous Drain Current: 0.5 A
• Power Dissipation: 300 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dynamic Characteristics
C
C
C
R
Switching Characteristics
t
t
t
t
Q
Q
Q
Electrical Characteristics
Off Characteristics
On Characteristics
Drain–Source Diode Characteristics and Maximum Ratings
Symbol
BV
I
I
V
R
I
g
I
V
Notes:
1. R
2. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%
d(on)
r
d(off)
f
Q
t
DSS
GSS
D(on)
S
iss
oss
rss
G
rr
FS
g
gs
gd
BV
GS(th)
V
SD
DS(on)
the drain pins. R
rr
DSS
GS(th)
T
T
JA
DSS
J
J
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
Reverse Recovery Time
Reverse Recovery Charge
JC
is guaranteed by design while R
Parameter
(Note 2)
(Note 2)
JA
is determined by the user's board design. R
V
I
V
V
I
V
V
V
V
V
V
f = 1.0 MHz
V
V
V
V
V
V
I
d
V
D
D
F
T
iF
GS
DS
GS
DS
GS
GS
GS
GS
DS
DS
GS
DD
GS
DS
GS
GS
= –0.5 A,
A
= –250 A, Referenced to 25 C
= –250 A, Referenced to 25 C
/d
= 25°C unless otherwise noted
= 0 V,
= –16 V, V
=
= V
= –4.5 V, I
= –2.5 V, I
= –4.5 V, I
= –4.5 V, V
= –5 V,
= –10 V, V
= 15 mV, f = 1.0 MHz
= –10 V, I
= –4.5 V, R
= –10 V, I
= –4.5 V
= 0 V,
t
= 100 A/µs
Test Conditions
GS
12 V, V
,
I
I
I
I
D
D
D
D
D
D
D
S
D
GEN
GS
DS
DS
GS
= –0.25 A
= –250 A
= –250 A
= –0.5 A
= –0.4 A
= –0.5 A, T
= –0.5 A
= –0.6 A,
= 1 A,
= 0 V
= –5 V
= 0 V
= 0 V,
= 6
(Note 2)
J
JA
=125°C
= 415°C/W when mounted on a minimum pad .
–0.65
Min
–1.8
–20
–0.83
Typ
–1.2
12.1
0.86
0.22
0.25
12.6
2.52
–10
580
980
780
1.1
83
20
11
12
2
6
6
1
–0.25
Max
1200
–1.5
–1.2
780
1.2
–1
100
12
22
13
FDG6318P Rev C (W)
3
Units
mV/ C
mV/ C
m
ns
nC
nA
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
V
A
S
A
V
A