HSP45102SC-40 Intersil, HSP45102SC-40 Datasheet
HSP45102SC-40
Specifications of HSP45102SC-40
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HSP45102SC-40 Summary of contents
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... PART MARKING HSP45102SC-33 HSP45102SC-33 HSP45102SC-33Z (Note) HSP45102SC-33Z HSP45102SC-40 HSP45102SC -40 HSP45102SC-40Z (Note) HSP45102SC-40Z HSP45102SI-3396 HSP45102SI -33 HSP45102SI-33Z (Note) HSP45102SI-33Z NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Block Diagram CLK PO-1 MSB/LSB SFTEN SD SCLK Pinout 2 HSP45102 32 FREQUENCY PHASE CONTROL 32 ACCUMULATOR 13 SECTION LOAD TXFR ENPHAC SEL_L/M HSP45102 (28 LEAD SOIC) TOP VIEW OUT6 1 OUT7 2 3 OUT8 OUT9 4 OUT10 5 OUT11 ...
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Pin Description NAME TYPE V CC GND P0-1 I CLK I SCLK I SEL_L/M I SFTEN I MSB/LSB I ENPHAC TXFR I LOAD I OUT0-11 O All inputs are TTL level, with the exception of CLK. Overline ...
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P0-1 R.P0-1 ENPHAC R.ENPHAC 4-DLY TXFR R.TXFR R E LOAD G CLK CLK SD SCLK SFTEN MSB/LSB SEL_L/M Functional Description The NCO12 produces a 12-bit sinusoid whose frequency and phase are digitally controlled. The frequency of the sine wave is ...
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At each clock, the contents of this register are summed with the current contents of the accumulator to step to the new phase. The phase accumulator stepping may be inhibited by holding ENPHAC high. The phase accumulator may ...
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... Output load per test load circuit with switch open and C 6 HSP45102 Thermal Information = +25°C Thermal Resistance (Typical, Note 1) +0.5V SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SYMBOL TEST CONDITIONS 5.25V ...
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AC Electrical Specifications V PARAMETER Clock Period Clock High Clock Low SCLK High/Low Setup Time SD to SCLK Going High Hold Time SD from SCLK Going High Setup Time SFTEN, MSB/LSB to SCLK Going High Hold Time SFTEN, MSB/LSB from ...
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Waveforms CLK P0-1 LOAD, TXFR, ENPHAC, SEL_L/M OUT0-11 SCLK SD MSB/LSB, SFTEN 8 HSP45102 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...