CY28329ZXC Silicon Laboratories Inc, CY28329ZXC Datasheet
CY28329ZXC
Specifications of CY28329ZXC
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CY28329ZXC Summary of contents
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MHz Spread Spectrum Clock Synthesizer/Driver Features • Multiple output clocks at different frequencies — Four pairs of differential CPU outputs 133 MHz — Ten synchronous PCI clocks, three free-running — Six 3V66 clocks — Two 48-MHz clocks ...
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Pin Description Name Pins REF 56 3.3V 14.318 MHz clock output XTAL_IN 2 14.318 MHz crystal input XTAL_OUT 3 14.318 MHz crystal input CPU, CPU [0:3]# 44, 45, 48, 49, Differential CPU clock outputs 51, 52, 53, 54 3V66_0 33 ...
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Function Table 66BUFF[0:2]/ CPU 3V66[0:1 (MHz) MHz 100 MHz 66 MHz 66IN 1 1 133 MHz 66 MHz 66IN 0 0 100 MHz 66 MHz 66 MHz 0 1 133 MHz 66 MHz 66 MHz ...
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Serial Data Interface (SMBus) To enhance the flexibility and function of the clock synthesizer, a two-signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc. can ...
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Data Byte 1: Bit Pin# Name Bit 7 – Bit 6 53, 54 CPU3 CPU3# Bit 5 – – Bit 4 – – Bit 3 – – Bit 2 44, 45 CPU2 CPU2# Bit 1 48, 49 CPU1 CPU1# Bit ...
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Data Byte 4: Bit Pin# Name Bit 7 – Bit 6 – Bit 5 33 3V66_0 Bit 4 35 3V66_1/VCH Bit 3 24 66IN/3V66_5 Bit 2 23 66BUFF2 Bit 1 22 66BUFF1 Bit 0 21 66BUFF0 Data Byte 5: Bit ...
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Absolute Maximum Conditions (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage............................................ –0. Operating Conditions over which electrical parameters are guaranteed Parameter ...
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Switching Characteristics Over the Operating Range Parameter Output t All Output Duty Cycle 1 t CPU Rise Time 2 t USB, REF, Rising Edge Rate 2 DOT t PCI, 3V66 Rising Edge Rate 2 t CPU Fall Time 3 t ...
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Definition and Application of VTTPWRGD# Signal Vtt VRM8.5 VTTPWRGD# CLOCK S0 GENERATOR S1 Rev 1.0, November 24, 2006 CPU VTTPWRGD# BSEL0 3.3V 3.3V NPN 10K 10K CY28329 BSEL1 3.3V 10K GMCH 10K Page ...
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Switching Waveforms Duty Cycle Timing (Single-Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew ...
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Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK VDD and POR Timing VDD POR Rev 1.0, November 24, 2006 1.5V ...
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VTTPWRGD# Timing Diagrams GND VRM 5/12V PWR_GD VID [3:0] BSEL [1:0] VTTPWRGD FROM VRM VCC CPU CORE VTTPWRGD VCC CLOCK GEN State 0 CLOCK STATE OFF CLOCK VCO OFF CLOCK OUTPUTS GND VRM 5/12V PWRGD VID [3:0] BSEL [1:0] PWRGD ...
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PD# Assertion 66BUFF PCI PCI_F (APIC) PD# CPU CPU# 3V66 66IN USB REF PD# Deassertion 66BUFF1/GMCH 66BUFF[0:2] PCI PCI_F (APIC) PD# CPU CPU# 3V66 66IN USB REF Rev 1.0, November 24, 2006 Power Down Rest of Generator 10–30 μs min. ...
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Layout Example +3.3V Supply FB 10 μF 0.005 μ VDDQ3 1.0 - 4.7KΩ Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S Ceramic Caps C1 = 10–22 μ VIA ...
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... Small Shrunk Outline Package (SSOP) CY28329OXCT 56-Pin Small Shrunk Outline Package (SSOP) -Tape and Reel CY28329ZXC 56-Pin Thin Small Shrunk Outline Package (TSSOP) CY28329ZXCT 56-Pin Thin Small Shrunk Outline Package (TSSOP) Rev 1.0, November 24, 2006 4, 9, 15, 20, 31, 36, 41 14, 19,32,37, 46, 50 ...
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Package Drawing and Dimensions 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra ...