CYW320OXC-3 Silicon Laboratories Inc, CYW320OXC-3 Datasheet
CYW320OXC-3
Specifications of CYW320OXC-3
Related parts for CYW320OXC-3
CYW320OXC-3 Summary of contents
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MHz Spread Spectrum Clock Synthesizer/Driver Features ® • Compliant with Intel CK-Titan Clock Synthe- sizer/Driver Specifications • Multiple output clocks at different frequencies • Three pairs of differential CPU outputs 200 MHz • Ten synchronous PCI clocks, ...
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Pin Summary Name Pins REF 56 XTAL_IN 2 XTAL_OUT 3 CPU, CPU# [0:2] 44, 45, 48, 49, 51, 52 3V66_0 33 3V66_1/VCH 35 66IN/3V66_5 24 66BUFF [2:0] /3V66 21, 22, 23 [4:2] PCI_F [0: PCI [0:6] 10, ...
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Function Table CPU 3V66[0: (MHz) (MHz MHz 66 MHz 100 MHz 66 MHz 200 MHz 66 MHz 133 MHz 66 MHz 0 0 ...
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Serial Data Interface (SMBus) To enhance the flexibility and function of the clock synthesizer, a two signal SMBus interface is provided according to the SMBus specification. Through the Serial Data Interface (SDI), various device functions such as individual clock output ...
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Data Byte 1 Bit Pin# Name Bit 7 – N/A Bit 6 – N/A Bit 5 44, 45 CPU2 CPU2# Bit 4 48, 49 CPU1 CPU1# Bit 3 51, 52 CPU0 CPU0# Bit 2 44, 45 CPU2 CPU2# Bit 1 ...
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Data Byte 4 Bit Pin# Name Bit 7 -- TBD Bit 6 -- TBD Bit 5 33 3V66_0 Bit 4 35 3V66_1/VCH Bit 3 24 66IN/3V66_5 Bit 2 23 66BUFF2 Bit 1 22 66BUFF1 Bit 0 21 66BUFF0 Data Byte ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage..................................................–0.5 to +7.0V Input Voltage.............................................. –0. Operating Conditions Over which Electrical Parameters are Guaranteed Parameter 3.3V ...
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Switching Characteristics Over the Operating Range Parameter Output t All Output Duty Cycle 1 t USB, REF, DOT Falling Edge Rate 3 t PCI,3V66 Falling Edge Rate 3 t 3V66[0:1] 3V66-3V66 Skew 5 t 66BUFF[0:2] 66BUFF-66BUFF Skew 5 t ...
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Definition and Application of PWRGD# Signal Vtt VRM8.5 PWRGD# CLOCK S0 GENERATOR S1 Rev 1.0, November 25, 2006 CPU PWRGD# BSEL0 3.3V 3.3V NPN 10K 10K W320-03 BSEL1 3.3V 10K GMCH 10K Page ...
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Switching Waveforms Duty Cycle Timing (Single Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock ...
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Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK [15] PWRDWN# Assertion 66BUFF PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: 15. PCI_STOP# asserted LOW. Rev ...
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PWRDWN# Deassertion 66BUFF1/GMCH 66BUFF0,2 PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF PWRGD# Timing Diagrams GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM NPN VCC CPU CORE PWRGD# VCC W320 CLOCK GEN ...
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GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM VCC CPU CORE PWRGD# 0.2 – 0.3 ms Wait for VCC W320 CLOCK delay PWRGD# GEN State 1 State 0 CLOCK STATE OFF CLOCK VCO OFF CLOCK ...
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Layout Example +3.3V Supply FB 10 μF 0.005 μ Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S Ceramic Caps C1 = 10–22 µ VIA to GND plane layer ...
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... Ordering Code W320-03H W320-03HT W320-03X W320-03XT Lead-free CYW320OXC-3 CYW320OXC-3T Notes: 16. Each supply pin must have an individual decoupling capacitor. 17. All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: R Rev 1.0, November 25, 2006 9, 15, 20, 27, 31, 36, 41 14, 26, 32, 37, 46, 50 W320-03 ...
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Package Diagrams 56-Lead Thin Shrunk Small Outline Package, Type mm) Z56 0.249[0.009 13.894[0.547] 14.097[0.555] 0.851[0.033] 0.500[0.020] 0.950[0.037] BSC While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes ...